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https://github.com/brain-hackers/u-boot-brain
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4dd4fc32db
The SoC feature init will be better to use arch_cpu_init() and goes to soc file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/grf_rk3188.h>
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#include <asm/arch-rockchip/hardware.h>
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#define GRF_BASE 0x20008000
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3188 */
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struct rk3188_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART2_SOUT,
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GPIO1B1_JTAG_TDO,
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GPIO1B0_SHIFT = 0,
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GPIO1B0_MASK = 3,
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GPIO1B0_GPIO = 0,
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GPIO1B0_UART2_SIN,
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GPIO1B0_JTAG_TDI,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK << GPIO1B1_SHIFT |
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GPIO1B0_MASK << GPIO1B0_SHIFT,
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GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
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GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_ROCKCHIP_USB_UART
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struct rk3188_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->uoc0_con[0],
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SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
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1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
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1 << COMMON_ON_N_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[2],
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SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[3],
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OPMODE_MASK | XCVRSELECT_MASK |
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TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
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OPMODE_NODRIVING << OPMODE_SHIFT |
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XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
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1 << TERMSEL_FULLSPEED_SHIFT |
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1 << SUSPENDN_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[0],
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BYPASSSEL_MASK | BYPASSDMEN_MASK,
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1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
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#endif
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return 0;
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}
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