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![Roger Quadros](/assets/img/avatar_default.png)
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
606 lines
16 KiB
C
606 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device.h>
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#include <generic-phy.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <syscon.h>
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#include <regmap.h>
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/* PLLCTRL Registers */
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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#define PLL_CONFIGURATION2 0x00000010
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#define PLL_CONFIGURATION3 0x00000014
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#define PLL_CONFIGURATION4 0x00000020
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#define PLL_REGM_MASK 0x001FFE00
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#define PLL_REGM_SHIFT 9
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#define PLL_REGM_F_MASK 0x0003FFFF
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#define PLL_REGM_F_SHIFT 0
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#define PLL_REGN_MASK 0x000001FE
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#define PLL_REGN_SHIFT 1
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#define PLL_SELFREQDCO_MASK 0x0000000E
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#define PLL_SELFREQDCO_SHIFT 1
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#define PLL_SD_MASK 0x0003FC00
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#define PLL_SD_SHIFT 10
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#define SET_PLL_GO 0x1
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#define PLL_TICOPWDN BIT(16)
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#define PLL_LDOPWDN BIT(15)
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#define PLL_LOCK 0x2
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#define PLL_IDLE 0x1
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/* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
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#define SATA_PLL_SOFT_RESET (1<<18)
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/* PHY POWER CONTROL Register */
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#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
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#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
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#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
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#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
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/* PHY RX Registers */
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#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
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#define INTERFACE_MASK GENMASK(31, 27)
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#define INTERFACE_SHIFT 27
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#define INTERFACE_MODE_USBSS BIT(4)
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#define INTERFACE_MODE_SATA_1P5 BIT(3)
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#define INTERFACE_MODE_SATA_3P0 BIT(2)
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#define INTERFACE_MODE_PCIE BIT(0)
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#define LOSD_MASK GENMASK(17, 14)
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#define LOSD_SHIFT 14
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#define MEM_PLLDIV GENMASK(6, 5)
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#define PIPE3_PHY_RX_TRIM 0x0000001C
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#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
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#define MEM_DLL_TRIM_SHIFT 30
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#define PIPE3_PHY_RX_DLL 0x00000024
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#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
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#define MEM_DLL_PHINT_RATE_SHIFT 30
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#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
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#define MEM_HS_RATE_MASK GENMASK(28, 27)
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#define MEM_HS_RATE_SHIFT 27
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#define MEM_OVRD_HS_RATE BIT(26)
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#define MEM_OVRD_HS_RATE_SHIFT 26
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#define MEM_CDR_FASTLOCK BIT(23)
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#define MEM_CDR_FASTLOCK_SHIFT 23
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#define MEM_CDR_LBW_MASK GENMASK(22, 21)
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#define MEM_CDR_LBW_SHIFT 21
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#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
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#define MEM_CDR_STEPCNT_SHIFT 19
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#define MEM_CDR_STL_MASK GENMASK(18, 16)
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#define MEM_CDR_STL_SHIFT 16
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#define MEM_CDR_THR_MASK GENMASK(15, 13)
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#define MEM_CDR_THR_SHIFT 13
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#define MEM_CDR_THR_MODE BIT(12)
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#define MEM_CDR_THR_MODE_SHIFT 12
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#define MEM_CDR_2NDO_SDM_MODE BIT(11)
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#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
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#define PIPE3_PHY_RX_EQUALIZER 0x00000038
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#define MEM_EQLEV_MASK GENMASK(31, 16)
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#define MEM_EQLEV_SHIFT 16
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#define MEM_EQFTC_MASK GENMASK(15, 11)
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#define MEM_EQFTC_SHIFT 11
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#define MEM_EQCTL_MASK GENMASK(10, 7)
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#define MEM_EQCTL_SHIFT 7
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#define MEM_OVRD_EQLEV BIT(2)
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#define MEM_OVRD_EQLEV_SHIFT 2
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#define MEM_OVRD_EQFTC BIT(1)
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#define MEM_OVRD_EQFTC_SHIFT 1
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#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
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#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
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#define MEM_CDR_LOS_SOURCE_SHIFT 9
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#define PLL_IDLE_TIME 100 /* in milliseconds */
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#define PLL_LOCK_TIME 100 /* in milliseconds */
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enum pipe3_mode { PIPE3_MODE_PCIE = 1,
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PIPE3_MODE_SATA,
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PIPE3_MODE_USBSS };
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struct pipe3_settings {
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u8 ana_interface;
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u8 ana_losd;
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u8 dig_fastlock;
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u8 dig_lbw;
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u8 dig_stepcnt;
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u8 dig_stl;
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u8 dig_thr;
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u8 dig_thr_mode;
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u8 dig_2ndo_sdm_mode;
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u8 dig_hs_rate;
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u8 dig_ovrd_hs_rate;
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u8 dll_trim_sel;
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u8 dll_phint_rate;
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u8 eq_lev;
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u8 eq_ftc;
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u8 eq_ctl;
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u8 eq_ovrd_lev;
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u8 eq_ovrd_ftc;
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};
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struct omap_pipe3 {
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void __iomem *pll_ctrl_base;
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void __iomem *phy_rx;
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void __iomem *power_reg;
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void __iomem *pll_reset_reg;
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struct pipe3_dpll_map *dpll_map;
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enum pipe3_mode mode;
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struct pipe3_settings settings;
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};
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struct pipe3_dpll_params {
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u16 m;
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u8 n;
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u8 freq:3;
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u8 sd;
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u32 mf;
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};
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struct pipe3_dpll_map {
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unsigned long rate;
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struct pipe3_dpll_params params;
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};
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struct pipe3_data {
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enum pipe3_mode mode;
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struct pipe3_dpll_map *dpll_map;
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struct pipe3_settings settings;
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};
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static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
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{
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return readl(addr + offset);
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}
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static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
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u32 data)
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{
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writel(data, addr + offset);
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}
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static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
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*pipe3)
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{
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u32 rate;
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struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
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rate = get_sys_clk_freq();
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
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__func__, rate);
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return NULL;
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}
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static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
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{
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u32 val;
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int timeout = PLL_LOCK_TIME;
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do {
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mdelay(1);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if (val & PLL_LOCK)
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break;
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} while (--timeout);
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if (!(val & PLL_LOCK)) {
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printf("%s: DPLL failed to lock\n", __func__);
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return -EBUSY;
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}
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return 0;
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}
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static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
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{
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u32 val;
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struct pipe3_dpll_params *dpll_params;
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dpll_params = omap_pipe3_get_dpll_params(pipe3);
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if (!dpll_params) {
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printf("%s: Invalid DPLL parameters\n", __func__);
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return -EINVAL;
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}
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
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val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGM_MASK;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
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val &= ~PLL_REGM_F_MASK;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
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val &= ~PLL_SD_MASK;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
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return omap_pipe3_wait_lock(pipe3);
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}
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static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
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{
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u32 val, rate;
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val = readl(pipe3->power_reg);
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rate = get_sys_clk_freq();
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rate = rate/1000000;
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if (on) {
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val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
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PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
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val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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writel(val, pipe3->power_reg);
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/* Power up TX before RX for SATA & USB */
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val |= PIPE3_PHY_TX_POWERON;
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writel(val, pipe3->power_reg);
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val |= PIPE3_PHY_RX_POWERON;
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writel(val, pipe3->power_reg);
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} else {
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val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
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writel(val, pipe3->power_reg);
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}
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}
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static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
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{
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u32 val;
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struct pipe3_settings *s = &phy->settings;
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
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val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
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val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
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val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
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MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
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MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
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val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
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s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
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s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
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s->dig_lbw << MEM_CDR_LBW_SHIFT |
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s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
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s->dig_stl << MEM_CDR_STL_SHIFT |
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s->dig_thr << MEM_CDR_THR_SHIFT |
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s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
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s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
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val &= ~MEM_DLL_TRIM_SEL_MASK;
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val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
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val &= ~MEM_DLL_PHINT_RATE_MASK;
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val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
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val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
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MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
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val |= s->eq_lev << MEM_EQLEV_SHIFT |
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s->eq_ftc << MEM_EQFTC_SHIFT |
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s->eq_ctl << MEM_EQCTL_SHIFT |
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s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
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s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
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if (phy->mode == PIPE3_MODE_SATA) {
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val = omap_pipe3_readl(phy->phy_rx,
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SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
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val &= ~MEM_CDR_LOS_SOURCE_MASK;
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omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
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val);
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}
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}
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static int pipe3_init(struct phy *phy)
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{
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int ret;
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u32 val;
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Program the DPLL only if not locked */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if (!(val & PLL_LOCK)) {
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ret = omap_pipe3_dpll_program(pipe3);
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if (ret)
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return ret;
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ti_pipe3_calibrate(pipe3);
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} else {
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/* else just bring it out of IDLE mode */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base,
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PLL_CONFIGURATION2);
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if (val & PLL_IDLE) {
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val &= ~PLL_IDLE;
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omap_pipe3_writel(pipe3->pll_ctrl_base,
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PLL_CONFIGURATION2, val);
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ret = omap_pipe3_wait_lock(pipe3);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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static int pipe3_power_on(struct phy *phy)
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{
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Power up the PHY */
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omap_control_pipe3_power(pipe3, 1);
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return 0;
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}
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static int pipe3_power_off(struct phy *phy)
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{
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Power down the PHY */
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omap_control_pipe3_power(pipe3, 0);
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return 0;
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}
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static int pipe3_exit(struct phy *phy)
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{
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u32 val;
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int timeout = PLL_IDLE_TIME;
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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pipe3_power_off(phy);
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/* Put DPLL in IDLE mode */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
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val |= PLL_IDLE;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
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/* wait for LDO and Oscillator to power down */
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do {
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mdelay(1);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
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break;
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} while (--timeout);
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if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
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pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
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__func__, val);
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return -EBUSY;
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}
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if (pipe3->pll_reset_reg) {
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val = readl(pipe3->pll_reset_reg);
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writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
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mdelay(1);
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writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
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}
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return 0;
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}
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static void *get_reg(struct udevice *dev, const char *name)
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{
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struct udevice *syscon;
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struct regmap *regmap;
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const fdt32_t *cell;
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int len, err;
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void *base;
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err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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name, &syscon);
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if (err) {
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pr_err("unable to find syscon device for %s (%d)\n",
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name, err);
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return NULL;
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}
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regmap = syscon_get_regmap(syscon);
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if (IS_ERR(regmap)) {
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pr_err("unable to find regmap for %s (%ld)\n",
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name, PTR_ERR(regmap));
|
|
return NULL;
|
|
}
|
|
|
|
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
|
|
&len);
|
|
if (len < 2*sizeof(fdt32_t)) {
|
|
pr_err("offset not available for %s\n", name);
|
|
return NULL;
|
|
}
|
|
|
|
base = regmap_get_range(regmap, 0);
|
|
if (!base)
|
|
return NULL;
|
|
|
|
return fdtdec_get_number(cell + 1, 1) + base;
|
|
}
|
|
|
|
static int pipe3_phy_probe(struct udevice *dev)
|
|
{
|
|
fdt_addr_t addr;
|
|
fdt_size_t sz;
|
|
struct omap_pipe3 *pipe3 = dev_get_priv(dev);
|
|
struct pipe3_data *data;
|
|
|
|
/* PHY_RX */
|
|
addr = devfdt_get_addr_size_index(dev, 0, &sz);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
pr_err("missing phy_rx address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
|
|
if (!pipe3->phy_rx) {
|
|
pr_err("unable to remap phy_rx\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* PLLCTRL */
|
|
addr = devfdt_get_addr_size_index(dev, 2, &sz);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
pr_err("missing pll ctrl address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
|
|
if (!pipe3->pll_ctrl_base) {
|
|
pr_err("unable to remap pll ctrl\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pipe3->power_reg = get_reg(dev, "syscon-phy-power");
|
|
if (!pipe3->power_reg)
|
|
return -EINVAL;
|
|
|
|
data = (struct pipe3_data *)dev_get_driver_data(dev);
|
|
pipe3->mode = data->mode;
|
|
pipe3->dpll_map = data->dpll_map;
|
|
pipe3->settings = data->settings;
|
|
|
|
if (pipe3->mode == PIPE3_MODE_SATA) {
|
|
pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
|
|
if (!pipe3->pll_reset_reg)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pipe3_dpll_map dpll_map_sata[] = {
|
|
{12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
|
|
{16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
|
|
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
|
|
{20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
|
|
{26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
|
|
{38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
|
|
{ }, /* Terminator */
|
|
};
|
|
|
|
static struct pipe3_dpll_map dpll_map_usb[] = {
|
|
{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
|
|
{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
|
|
{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
|
|
{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
|
|
{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
|
|
{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
|
|
{ }, /* Terminator */
|
|
};
|
|
|
|
static struct pipe3_data data_usb = {
|
|
.mode = PIPE3_MODE_USBSS,
|
|
.dpll_map = dpll_map_usb,
|
|
.settings = {
|
|
/* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
|
|
.ana_interface = INTERFACE_MODE_USBSS,
|
|
.ana_losd = 0xa,
|
|
.dig_fastlock = 1,
|
|
.dig_lbw = 3,
|
|
.dig_stepcnt = 0,
|
|
.dig_stl = 0x3,
|
|
.dig_thr = 1,
|
|
.dig_thr_mode = 1,
|
|
.dig_2ndo_sdm_mode = 0,
|
|
.dig_hs_rate = 0,
|
|
.dig_ovrd_hs_rate = 1,
|
|
.dll_trim_sel = 0x2,
|
|
.dll_phint_rate = 0x3,
|
|
.eq_lev = 0,
|
|
.eq_ftc = 0,
|
|
.eq_ctl = 0x9,
|
|
.eq_ovrd_lev = 0,
|
|
.eq_ovrd_ftc = 0,
|
|
},
|
|
};
|
|
|
|
static struct pipe3_data data_sata = {
|
|
.mode = PIPE3_MODE_SATA,
|
|
.dpll_map = dpll_map_sata,
|
|
.settings = {
|
|
/* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
|
|
.ana_interface = INTERFACE_MODE_SATA_3P0,
|
|
.ana_losd = 0x5,
|
|
.dig_fastlock = 1,
|
|
.dig_lbw = 3,
|
|
.dig_stepcnt = 0,
|
|
.dig_stl = 0x3,
|
|
.dig_thr = 1,
|
|
.dig_thr_mode = 1,
|
|
.dig_2ndo_sdm_mode = 0,
|
|
.dig_hs_rate = 0, /* Not in TRM preferred settings */
|
|
.dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
|
|
.dll_trim_sel = 0x1,
|
|
.dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
|
|
.eq_lev = 0,
|
|
.eq_ftc = 0x1f,
|
|
.eq_ctl = 0,
|
|
.eq_ovrd_lev = 1,
|
|
.eq_ovrd_ftc = 1,
|
|
},
|
|
};
|
|
|
|
static const struct udevice_id pipe3_phy_ids[] = {
|
|
{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
|
|
{ .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
|
|
{ }
|
|
};
|
|
|
|
static struct phy_ops pipe3_phy_ops = {
|
|
.init = pipe3_init,
|
|
.power_on = pipe3_power_on,
|
|
.power_off = pipe3_power_off,
|
|
.exit = pipe3_exit,
|
|
};
|
|
|
|
U_BOOT_DRIVER(pipe3_phy) = {
|
|
.name = "pipe3_phy",
|
|
.id = UCLASS_PHY,
|
|
.of_match = pipe3_phy_ids,
|
|
.ops = &pipe3_phy_ops,
|
|
.probe = pipe3_phy_probe,
|
|
.priv_auto_alloc_size = sizeof(struct omap_pipe3),
|
|
};
|