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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
179 lines
5.1 KiB
C
179 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx AXI Bridge for PCI Express Driver
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*
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* Copyright (C) 2016 Imagination Technologies
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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/**
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* struct xilinx_pcie - Xilinx PCIe controller state
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* @cfg_base: The base address of memory mapped configuration space
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*/
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struct xilinx_pcie {
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void *cfg_base;
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};
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/* Register definitions */
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#define XILINX_PCIE_REG_PSCR 0x144
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#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
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/**
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* pcie_xilinx_link_up() - Check whether the PCIe link is up
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* @pcie: Pointer to the PCI controller state
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*
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* Checks whether the PCIe link for the given device is up or down.
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*
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* Return: true if the link is up, else false
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*/
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static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
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{
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uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
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return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
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}
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/**
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* pcie_xilinx_config_address() - Calculate the address of a config access
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* @udev: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @paddress: Pointer to the pointer to write the calculates address to
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*
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* Calculates the address that should be accessed to perform a PCIe
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* configuration space access for a given device identified by the PCIe
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* controller device @pcie and the bus, device & function numbers in @bdf. If
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* access to the device is not valid then the function will return an error
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* code. Otherwise the address to access will be written to the pointer pointed
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* to by @paddress.
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*
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* Return: 0 on success, else -ENODEV
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*/
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static int pcie_xilinx_config_address(struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct xilinx_pcie *pcie = dev_get_priv(udev);
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int func = PCI_FUNC(bdf);
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void *addr;
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if ((bus > 0) && !pcie_xilinx_link_up(pcie))
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return -ENODEV;
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/*
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* Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
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* limited to a single device each.
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*/
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if ((bus < 2) && (dev > 0))
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return -ENODEV;
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addr = pcie->cfg_base;
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addr += bus << 20;
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addr += dev << 15;
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addr += func << 12;
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addr += offset;
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*paddress = addr;
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return 0;
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}
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/**
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* pcie_xilinx_read_config() - Read from configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*
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* Return: 0 on success, else -ENODEV or -EINVAL
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*/
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static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
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bdf, offset, valuep, size);
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}
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/**
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* pcie_xilinx_write_config() - Write to configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*
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* Return: 0 on success, else -ENODEV or -EINVAL
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*/
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static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
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bdf, offset, value, size);
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}
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/**
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* pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
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* @dev: A pointer to the device being operated on
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*
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* Translate relevant data from the device tree pertaining to device @dev into
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* state that the driver will later make use of. This state is stored in the
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* device's private data structure.
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*
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* Return: 0 on success, else -EINVAL
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*/
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static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
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{
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struct xilinx_pcie *pcie = dev_get_priv(dev);
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struct fdt_resource reg_res;
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DECLARE_GLOBAL_DATA_PTR;
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int err;
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err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
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0, ®_res);
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if (err < 0) {
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pr_err("\"reg\" resource not found\n");
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return err;
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}
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pcie->cfg_base = map_physmem(reg_res.start,
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fdt_resource_size(®_res),
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MAP_NOCACHE);
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return 0;
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}
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static const struct dm_pci_ops pcie_xilinx_ops = {
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.read_config = pcie_xilinx_read_config,
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.write_config = pcie_xilinx_write_config,
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};
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static const struct udevice_id pcie_xilinx_ids[] = {
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{ .compatible = "xlnx,axi-pcie-host-1.00.a" },
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{ }
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};
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U_BOOT_DRIVER(pcie_xilinx) = {
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.name = "pcie_xilinx",
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.id = UCLASS_PCI,
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.of_match = pcie_xilinx_ids,
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.ops = &pcie_xilinx_ops,
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.ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct xilinx_pcie),
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};
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