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![Simon Glass](/assets/img/avatar_default.png)
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
273 lines
5.9 KiB
C
273 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI emulation device for an x86 Primary-to-Sideband bus
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*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#define LOG_CATEGORY UCLASS_MISC
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#define LOG_DEBUG
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#include <common.h>
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#include <axi.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/test.h>
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#include <p2sb.h>
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/**
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* struct p2sb_emul_platdata - platform data for this device
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*
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* @command: Current PCI command value
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* @bar: Current base address values
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*/
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struct p2sb_emul_platdata {
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u16 command;
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u32 bar[6];
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};
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enum {
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/* This emulator supports 16 different devices */
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MEMMAP_SIZE = 16 << PCR_PORTID_SHIFT,
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};
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static struct pci_bar {
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int type;
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u32 size;
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} barinfo[] = {
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{ PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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};
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struct p2sb_emul_priv {
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u8 regs[16];
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};
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static int sandbox_p2sb_emul_read_config(struct udevice *emul, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
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switch (offset) {
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case PCI_COMMAND:
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*valuep = plat->command;
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break;
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case PCI_HEADER_TYPE:
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*valuep = PCI_HEADER_TYPE_NORMAL;
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break;
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case PCI_VENDOR_ID:
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*valuep = SANDBOX_PCI_VENDOR_ID;
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break;
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case PCI_DEVICE_ID:
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*valuep = SANDBOX_PCI_P2SB_EMUL_ID;
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break;
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case PCI_CLASS_DEVICE:
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if (size == PCI_SIZE_8) {
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*valuep = SANDBOX_PCI_CLASS_SUB_CODE;
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} else {
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*valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
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SANDBOX_PCI_CLASS_SUB_CODE;
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}
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break;
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case PCI_CLASS_CODE:
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*valuep = SANDBOX_PCI_CLASS_CODE;
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break;
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5: {
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int barnum;
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u32 *bar;
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barnum = pci_offset_to_barnum(offset);
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bar = &plat->bar[barnum];
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*valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
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barinfo[barnum].size);
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break;
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}
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case PCI_CAPABILITY_LIST:
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*valuep = PCI_CAP_ID_PM_OFFSET;
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break;
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}
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return 0;
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}
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static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset,
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ulong value, enum pci_size_t size)
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{
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struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
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switch (offset) {
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case PCI_COMMAND:
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plat->command = value;
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break;
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1: {
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int barnum;
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u32 *bar;
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barnum = pci_offset_to_barnum(offset);
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bar = &plat->bar[barnum];
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log_debug("w bar %d=%lx\n", barnum, value);
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*bar = value;
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/* space indicator (bit#0) is read-only */
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*bar |= barinfo[barnum].type;
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break;
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}
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}
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return 0;
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}
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static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr,
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int *barnump, unsigned int *offsetp)
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{
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struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
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int barnum;
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for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
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unsigned int size = barinfo[barnum].size;
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u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
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if (addr >= base && addr < base + size) {
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*barnump = barnum;
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*offsetp = addr - base;
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return 0;
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}
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}
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*barnump = -1;
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return -ENOENT;
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}
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static int sandbox_p2sb_emul_read_io(struct udevice *dev, unsigned int addr,
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ulong *valuep, enum pci_size_t size)
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{
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unsigned int offset;
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int barnum;
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int ret;
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ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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if (barnum == 4)
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*valuep = offset;
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else if (barnum == 0)
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*valuep = offset;
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return 0;
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}
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static int sandbox_p2sb_emul_write_io(struct udevice *dev, unsigned int addr,
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ulong value, enum pci_size_t size)
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{
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unsigned int offset;
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int barnum;
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int ret;
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ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return ret;
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return 0;
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}
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static int find_p2sb_channel(struct udevice *emul, uint offset,
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struct udevice **devp)
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{
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uint pid = offset >> PCR_PORTID_SHIFT;
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struct udevice *p2sb, *dev;
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int ret;
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ret = sandbox_pci_get_client(emul, &p2sb);
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if (ret)
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return log_msg_ret("No client", ret);
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device_foreach_child(dev, p2sb) {
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struct p2sb_child_platdata *pplat =
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dev_get_parent_platdata(dev);
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log_debug(" - child %s, pid %d, want %d\n", dev->name,
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pplat->pid, pid);
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if (pid == pplat->pid) {
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*devp = dev;
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return 0;
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}
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}
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return -ENOENT;
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}
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static int sandbox_p2sb_emul_map_physmem(struct udevice *dev,
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phys_addr_t addr, unsigned long *lenp,
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void **ptrp)
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{
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struct p2sb_emul_priv *priv = dev_get_priv(dev);
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struct udevice *child;
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unsigned int offset;
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int barnum;
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int ret;
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log_debug("map %x: ", (uint)addr);
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ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
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if (ret)
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return log_msg_ret("Cannot find bar", ret);
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log_debug("bar %d, offset %x\n", barnum, offset);
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if (barnum != 0)
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return log_msg_ret("Unknown BAR", -EINVAL);
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ret = find_p2sb_channel(dev, offset, &child);
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if (ret)
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return log_msg_ret("Cannot find channel", ret);
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offset &= ((1 << PCR_PORTID_SHIFT) - 1);
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ret = axi_read(child, offset, priv->regs, AXI_SIZE_32);
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if (ret)
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return log_msg_ret("Child read failed", ret);
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*ptrp = priv->regs + (offset & 3);
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*lenp = 4;
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return 0;
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}
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static struct dm_pci_emul_ops sandbox_p2sb_emul_emul_ops = {
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.read_config = sandbox_p2sb_emul_read_config,
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.write_config = sandbox_p2sb_emul_write_config,
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.read_io = sandbox_p2sb_emul_read_io,
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.write_io = sandbox_p2sb_emul_write_io,
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.map_physmem = sandbox_p2sb_emul_map_physmem,
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};
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static const struct udevice_id sandbox_p2sb_emul_ids[] = {
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{ .compatible = "sandbox,p2sb-emul" },
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{ }
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};
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U_BOOT_DRIVER(sandbox_p2sb_emul_emul) = {
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.name = "sandbox_p2sb_emul_emul",
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.id = UCLASS_PCI_EMUL,
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.of_match = sandbox_p2sb_emul_ids,
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.ops = &sandbox_p2sb_emul_emul_ops,
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.priv_auto_alloc_size = sizeof(struct p2sb_emul_priv),
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.platdata_auto_alloc_size = sizeof(struct p2sb_emul_platdata),
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};
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static struct pci_device_id sandbox_p2sb_emul_supported[] = {
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{ PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) },
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{},
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};
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U_BOOT_PCI_DEVICE(sandbox_p2sb_emul_emul, sandbox_p2sb_emul_supported);
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