mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 21:09:00 +09:00
![]() Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> |
||
---|---|---|
.. | ||
analogbits-wrpll-cln28hpc.h | ||
fu540-prci.c | ||
Kconfig | ||
Makefile | ||
wrpll-cln28hpc.c |