mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
![Kumar Gala](/assets/img/avatar_default.png)
There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
419 lines
9.9 KiB
C
419 lines
9.9 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <lmb.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_my_id()
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{
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return mfspr(SPRN_PIR);
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}
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/*
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* Determine if U-Boot should keep secondary cores in reset, or let them out
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* of reset and hold them in a spinloop
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*/
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int hold_cores_in_reset(int verbose)
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{
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const char *s = getenv("mp_holdoff");
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/* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
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if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
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if (verbose) {
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puts("Secondary cores are being held in reset.\n");
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puts("See 'mp_holdoff' environment variable\n");
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}
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return 1;
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}
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return 0;
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}
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int cpu_reset(int nr)
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{
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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out_be32(&pic->pir, 1 << nr);
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/* the dummy read works around an errata on early 85xx MP PICs */
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(void)in_be32(&pic->pir);
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out_be32(&pic->pir, 0x0);
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return 0;
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}
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int cpu_status(int nr)
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{
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u32 *table, id = get_my_id();
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if (hold_cores_in_reset(1))
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return 0;
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if (nr == id) {
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table = (u32 *)get_spin_virt_addr();
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printf("table base @ 0x%p\n", table);
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} else {
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table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
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printf("Running on cpu %d\n", id);
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printf("\n");
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printf("table @ 0x%p\n", table);
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printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
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printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
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printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
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printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
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}
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return 0;
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}
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#ifdef CONFIG_FSL_CORENET
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int cpu_disable(int nr)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->coredisrl, 1 << nr);
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return 0;
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}
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int is_core_disabled(int nr) {
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 coredisrl = in_be32(&gur->coredisrl);
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return (coredisrl & (1 << nr));
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}
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#else
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int cpu_disable(int nr)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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switch (nr) {
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case 0:
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
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break;
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case 1:
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
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break;
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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return 1;
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}
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return 0;
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}
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int is_core_disabled(int nr) {
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr = in_be32(&gur->devdisr);
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switch (nr) {
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case 0:
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return (devdisr & MPC85xx_DEVDISR_CPU0);
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case 1:
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return (devdisr & MPC85xx_DEVDISR_CPU1);
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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}
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return 0;
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}
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#endif
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static u8 boot_entry_map[4] = {
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0,
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BOOT_ENTRY_PIR,
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BOOT_ENTRY_R3_LOWER,
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BOOT_ENTRY_R6_LOWER,
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};
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int cpu_release(int nr, int argc, char * const argv[])
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{
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u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
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u64 boot_addr;
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if (hold_cores_in_reset(1))
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return 0;
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if (nr == get_my_id()) {
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printf("Invalid to release the boot core.\n\n");
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return 1;
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}
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if (argc != 4) {
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printf("Invalid number of arguments to release.\n\n");
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return 1;
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}
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boot_addr = simple_strtoull(argv[0], NULL, 16);
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/* handle pir, r3, r6 */
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for (i = 1; i < 4; i++) {
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if (argv[i][0] != '-') {
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u8 entry = boot_entry_map[i];
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val = simple_strtoul(argv[i], NULL, 16);
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table[entry] = val;
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}
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}
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table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
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/* ensure all table updates complete before final address write */
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eieio();
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table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
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return 0;
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}
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u32 determine_mp_bootpg(void)
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{
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/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
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if ((u64)gd->ram_size > 0xfffff000)
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return (0xfffff000);
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return (gd->ram_size - 4096);
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}
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ulong get_spin_phys_addr(void)
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{
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extern ulong __secondary_start_page;
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extern ulong __spin_table;
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return (determine_mp_bootpg() +
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(ulong)&__spin_table - (ulong)&__secondary_start_page);
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}
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ulong get_spin_virt_addr(void)
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{
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extern ulong __secondary_start_page;
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extern ulong __spin_table;
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return (CONFIG_BPTR_VIRT_ADDR +
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(ulong)&__spin_table - (ulong)&__secondary_start_page);
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}
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#ifdef CONFIG_FSL_CORENET
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static void plat_mp_up(unsigned long bootpg)
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{
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u32 up, cpu_up_mask, whoami;
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u32 *table = (u32 *)get_spin_virt_addr();
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volatile ccsr_gur_t *gur;
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volatile ccsr_local_t *ccm;
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volatile ccsr_rcpm_t *rcpm;
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volatile ccsr_pic_t *pic;
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int timeout = 10;
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u32 nr_cpus;
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struct law_entry e;
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gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
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rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
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whoami = in_be32(&pic->whoami);
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cpu_up_mask = 1 << whoami;
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out_be32(&ccm->bstrl, bootpg);
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e = find_law(bootpg);
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out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
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/* readback to sync write */
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in_be32(&ccm->bstrar);
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/* disable time base at the platform */
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out_be32(&rcpm->ctbenrl, cpu_up_mask);
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/* release the hounds */
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up = ((1 << nr_cpus) - 1);
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out_be32(&gur->brrl, up);
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/* wait for everyone */
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while (timeout) {
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int i;
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for (i = 0; i < nr_cpus; i++) {
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if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
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cpu_up_mask |= (1 << i);
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};
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if ((cpu_up_mask & up) == up)
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break;
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udelay(100);
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timeout--;
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}
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if (timeout == 0)
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printf("CPU up timeout. CPU up mask is %x should be %x\n",
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cpu_up_mask, up);
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/* enable time base at the platform */
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out_be32(&rcpm->ctbenrl, 0);
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/* readback to sync write */
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in_be32(&rcpm->ctbenrl);
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mtspr(SPRN_TBWU, 0);
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mtspr(SPRN_TBWL, 0);
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out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
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#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
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/*
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* Disabling Boot Page Translation allows the memory region 0xfffff000
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* to 0xffffffff to be used normally. Leaving Boot Page Translation
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* enabled remaps 0xfffff000 to SDRAM which makes that memory region
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* unusable for normal operation but it does allow OSes to easily
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* reset a processor core to put it back into U-Boot's spinloop.
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*/
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clrbits_be32(&ccm->bstrar, LAW_EN);
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#endif
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}
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#else
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static void plat_mp_up(unsigned long bootpg)
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{
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u32 up, cpu_up_mask, whoami;
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u32 *table = (u32 *)get_spin_virt_addr();
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volatile u32 bpcr;
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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u32 devdisr;
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int timeout = 10;
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whoami = in_be32(&pic->whoami);
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out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
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/* disable time base at the platform */
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devdisr = in_be32(&gur->devdisr);
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if (whoami)
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devdisr |= MPC85xx_DEVDISR_TB0;
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else
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devdisr |= MPC85xx_DEVDISR_TB1;
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out_be32(&gur->devdisr, devdisr);
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/* release the hounds */
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up = ((1 << cpu_numcores()) - 1);
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bpcr = in_be32(&ecm->eebpcr);
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bpcr |= (up << 24);
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out_be32(&ecm->eebpcr, bpcr);
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asm("sync; isync; msync");
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cpu_up_mask = 1 << whoami;
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/* wait for everyone */
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while (timeout) {
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int i;
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for (i = 0; i < cpu_numcores(); i++) {
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if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
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cpu_up_mask |= (1 << i);
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};
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if ((cpu_up_mask & up) == up)
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break;
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udelay(100);
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timeout--;
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}
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if (timeout == 0)
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printf("CPU up timeout. CPU up mask is %x should be %x\n",
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cpu_up_mask, up);
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/* enable time base at the platform */
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if (whoami)
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devdisr |= MPC85xx_DEVDISR_TB1;
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else
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devdisr |= MPC85xx_DEVDISR_TB0;
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out_be32(&gur->devdisr, devdisr);
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/* readback to sync write */
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in_be32(&gur->devdisr);
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mtspr(SPRN_TBWU, 0);
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mtspr(SPRN_TBWL, 0);
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devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
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out_be32(&gur->devdisr, devdisr);
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#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
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/*
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* Disabling Boot Page Translation allows the memory region 0xfffff000
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* to 0xffffffff to be used normally. Leaving Boot Page Translation
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* enabled remaps 0xfffff000 to SDRAM which makes that memory region
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* unusable for normal operation but it does allow OSes to easily
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* reset a processor core to put it back into U-Boot's spinloop.
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*/
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clrbits_be32(&ecm->bptr, 0x80000000);
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#endif
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}
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#endif
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void cpu_mp_lmb_reserve(struct lmb *lmb)
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{
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u32 bootpg = determine_mp_bootpg();
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lmb_reserve(lmb, bootpg, 4096);
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}
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void setup_mp(void)
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{
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extern ulong __secondary_start_page;
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extern ulong __bootpg_addr;
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ulong fixup = (ulong)&__secondary_start_page;
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u32 bootpg = determine_mp_bootpg();
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/* Some OSes expect secondary cores to be held in reset */
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if (hold_cores_in_reset(0))
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return;
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/* Store the bootpg's SDRAM address for use by secondary CPU cores */
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__bootpg_addr = bootpg;
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/* look for the tlb covering the reset page, there better be one */
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int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
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/* we found a match */
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if (i != -1) {
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/* map reset page to bootpg so we can copy code there */
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disable_tlb(i);
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set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
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memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
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plat_mp_up(bootpg);
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} else {
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puts("WARNING: No reset page TLB. "
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"Skipping secondary core setup\n");
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}
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}
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