mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
9c653aad16
Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
182 lines
5.0 KiB
C
182 lines
5.0 KiB
C
/*
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* Config file for Compulab CM-T335 board
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*
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* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Ilya Ledvich <ilya@compulab.co.il>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_CM_T335_H
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#define __CONFIG_CM_T335_H
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#define CONFIG_CM_T335
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#define CONFIG_NAND
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#include <configs/ti_am335x_common.h>
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#undef CONFIG_BOARD_LATE_INIT
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#undef CONFIG_SPI
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#undef CONFIG_OMAP3_SPI
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#undef CONFIG_CMD_SPI
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#undef CONFIG_SPL_OS_BOOT
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#undef CONFIG_BOOTCOUNT_LIMIT
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#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
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#undef CONFIG_MAX_RAM_BANK_SIZE
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
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#undef CONFIG_SYS_PROMPT
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#define CONFIG_SYS_PROMPT "CM-T335 # "
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#define CONFIG_OMAP_COMMON
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#define MACH_TYPE_CM_T335 4586 /* Until the next sync */
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#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
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/* Clock Defines */
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#define V_OSCK 25000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK)
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#ifndef CONFIG_SPL_BUILD
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#define MMCARGS \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
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"mmcrootfstype=ext4\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0"
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#define NANDARGS \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"nandroot=ubi0:rootfs rw\0" \
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"nandrootfstype=ubifs\0" \
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"nandargs=setenv bootargs console=${console} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype} " \
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"ubi.mtd=${rootfs_name}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nboot ${loadaddr} nand0 900000; " \
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"bootm ${loadaddr}\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=82000000\0" \
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"console=ttyO0,115200n8\0" \
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"rootfs_name=rootfs\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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MMCARGS \
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NANDARGS
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_TIMESTAMP
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#define CONFIG_SYS_AUTOLOAD "no"
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/* Serial console configuration */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SERIAL1 1 /* UART0 */
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/* NS16550 Configuration */
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#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
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#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
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#define CONFIG_BAUDRATE 115200
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/* I2C Configuration */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/* SPL */
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* NAND support */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#undef CONFIG_SYS_NAND_U_BOOT_OFFS
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
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#define CONFIG_CMD_NAND
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#define GPMC_NAND_ECC_LP_x8_LAYOUT
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
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"1m(u-boot),1m(u-boot-env)," \
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"1m(dtb),4m(splash)," \
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"6m(kernel),-(rootfs)"
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* GPIO pin + bank to pin ID mapping */
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#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
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/* Status LED */
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#define CONFIG_STATUS_LED
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#define CONFIG_GPIO_LED
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#define CONFIG_BOARD_SPECIFIC_LED
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#define STATUS_LED_BIT GPIO_PIN(2, 0)
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/* Status LED polarity is inversed, so init it in the "off" state */
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#define STATUS_LED_STATE STATUS_LED_OFF
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BOOT 0
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#ifndef CONFIG_SPL_BUILD
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/*
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* Enable PCA9555 at I2C0-0x26.
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* First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
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*/
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#define CONFIG_PCA953X
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#define CONFIG_CMD_PCA953X
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#define CONFIG_CMD_PCA953X_INFO
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#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
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#endif /* CONFIG_SPL_BUILD */
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#endif /* __CONFIG_CM_T335_H */
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