mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
255 lines
6.3 KiB
C
255 lines
6.3 KiB
C
/* Initializes CPU and basic hardware such as memory
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* controllers, IRQ controller and system timer 0.
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*
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* (C) Copyright 2007
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* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/asi.h>
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#include <asm/leon.h>
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#include <ambapp.h>
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#include <config.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* reset CPU (jump to 0, without reset) */
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void start(void);
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/* find & initialize the memory controller */
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int init_memory_ctrl(void);
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ambapp_dev_irqmp *irqmp = NULL;
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ambapp_dev_mctrl memctrl;
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ambapp_dev_gptimer *gptimer = NULL;
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unsigned int gptimer_irq = 0;
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int leon3_snooping_avail = 0;
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struct {
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gd_t gd_area;
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bd_t bd;
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} global_data;
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers.
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*
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* Run from FLASH/PROM:
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* - until memory controller is set up, only registers avaiable
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* - no global variables available for writing
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* - constants avaiable
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*/
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void cpu_init_f(void)
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{
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/* these varaiable must not be initialized */
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ambapp_dev_irqmp *irqmp;
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ambapp_apbdev apbdev;
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register unsigned int apbmst;
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/* find AMBA APB Master */
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apbmst = (unsigned int)
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ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_APBMST, 1, 0);
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if (!apbmst) {
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/*
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* no AHB/APB bridge, something is wrong
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* ==> jump to start (or hang)
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*/
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while (1) ;
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}
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/* Init memory controller */
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if (init_memory_ctrl()) {
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while (1) ;
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}
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/****************************************************
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* From here we can use the main memory and the stack.
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*/
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/* Find AMBA APB IRQMP Controller */
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if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev) != 1) {
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/* no IRQ controller, something is wrong
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* ==> jump to start (or hang)
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*/
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while (1) ;
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}
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irqmp = (ambapp_dev_irqmp *) apbdev.address;
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/* initialize the IRQMP */
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irqmp->ilevel = 0xf; /* all IRQ off */
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irqmp->iforce = 0;
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irqmp->ipend = 0;
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irqmp->iclear = 0xfffe; /* clear all old pending interrupts */
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irqmp->cpu_mask[0] = 0; /* mask all IRQs on CPU 0 */
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irqmp->cpu_force[0] = 0; /* no force IRQ on CPU 0 */
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/* cache */
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}
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void cpu_init_f2(void)
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{
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r(void)
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{
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ambapp_apbdev apbdev;
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/*
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* Find AMBA APB IRQMP Controller,
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* When we come so far we know there is a IRQMP available
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*/
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ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev);
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irqmp = (ambapp_dev_irqmp *) apbdev.address;
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/* timer */
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if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_GPTIMER, &apbdev) != 1) {
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printf("cpu_init_r: gptimer not found!\n");
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return 1;
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}
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gptimer = (ambapp_dev_gptimer *) apbdev.address;
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gptimer_irq = apbdev.irq;
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/* initialize prescaler common to all timers to 1MHz */
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gptimer->scalar = gptimer->scalar_reload =
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(((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
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return (0);
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}
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/* find & setup memory controller */
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int init_memory_ctrl()
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{
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register ambapp_dev_mctrl *mctrl;
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register ambapp_dev_sdctrl *sdctrl;
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register ambapp_dev_ddrspa *ddrspa;
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register ambapp_dev_ddr2spa *ddr2spa;
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register ahbctrl_pp_dev *ahb;
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register unsigned int base;
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register int not_found_mctrl = -1;
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/* find ESA Memory controller */
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base = ambapp_apb_next_nomem(VENDOR_ESA, ESA_MCTRL, 0);
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if (base) {
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mctrl = (ambapp_dev_mctrl *) base;
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/* config MCTRL memory controller */
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mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
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mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2;
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mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3;
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not_found_mctrl = 0;
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}
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/* find Gaisler Fault Tolerant Memory controller */
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base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_FTMCTRL, 0);
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if (base) {
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mctrl = (ambapp_dev_mctrl *) base;
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/* config MCTRL memory controller */
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mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
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mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2;
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mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3;
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not_found_mctrl = 0;
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}
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/* find SDRAM controller */
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base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_SDCTRL, 0);
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if (base) {
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sdctrl = (ambapp_dev_sdctrl *) base;
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/* config memory controller */
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sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM;
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not_found_mctrl = 0;
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}
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ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDR2SPA, 1, 0);
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if (ahb) {
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ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1);
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/* Config DDR2 memory controller */
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ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1;
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ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3;
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not_found_mctrl = 0;
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}
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ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDRSPA, 1, 0);
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if (ahb) {
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ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1);
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/* Config DDR memory controller */
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ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG;
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not_found_mctrl = 0;
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}
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/* failed to find any memory controller */
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return not_found_mctrl;
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}
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/* Uses Timer 0 to get accurate
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* pauses. Max 2 raised to 32 ticks
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*
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*/
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void cpu_wait_ticks(unsigned long ticks)
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{
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unsigned long start = get_timer(0);
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while (get_timer(start) < ticks) ;
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}
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/* initiate and setup timer0 interrupt to 1MHz
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* Return irq number for timer int or a negative number for
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* dealing with self
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*/
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int timer_interrupt_init_cpu(void)
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{
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/* 1ms ticks */
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gptimer->e[0].val = 0;
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gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */
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gptimer->e[0].ctrl =
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(LEON3_GPTIMER_EN |
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LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
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return gptimer_irq;
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}
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/*
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* This function is intended for SHORT delays only.
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*/
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unsigned long cpu_usec2ticks(unsigned long usec)
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{
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/* timer set to 1kHz ==> 1 clk tick = 1 msec */
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if (usec < 1000)
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return 1;
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return (usec / 1000);
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}
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unsigned long cpu_ticks2usec(unsigned long ticks)
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{
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/* 1tick = 1usec */
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return ticks * 1000;
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}
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