mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
4d13cbad1c
Fix early board initialization for Cogent CSB272 board * Patch by Ed Okerson, 3 Mar 2004: fix CFI flash writes for little endian systems * Patch by Reinhard Meyer, 01 Mar 2004: generalize USB and IDE support for MPC5200 with according changes to IceCube.h and TOP5200.h add Am29LV256 256 MBit FLASH support for TOP5200 boards add info about USB and IDE to README
314 lines
9.3 KiB
C
314 lines
9.3 KiB
C
/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
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#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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/*
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* OS Bootstrap configuration
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*
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*/
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
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#if 1
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/ram rw ramdisk_size=4096 " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm fe000000 fe100000"
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#endif
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#if 0
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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#endif
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/*
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* BOOTP/DHCP protocol configuration
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*
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*/
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#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_DNS2 | \
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CONFIG_BOOTP_BOOTFILESIZE )
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/*
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* U-Boot Monitor Command Line Functions Configuration
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*
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*/
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_ELF | \
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CFG_CMD_IRQ | \
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CFG_CMD_I2C | \
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CFG_CMD_PCI | \
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CFG_CMD_DATE | \
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CFG_CMD_MII | \
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CFG_CMD_PING | \
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CFG_CMD_DHCP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Serial download configuration
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*
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* KGDB Configuration
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*
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*
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*/
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#undef CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
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#endif
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
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#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* watchdog configuration
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*
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*/
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* UART configuration
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*
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*/
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#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
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#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
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#undef CFG_BASE_BAUD
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#define CONFIG_BAUDRATE 38400 /* Default baud rate */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* I2C configuration
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*
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 100000 /* I2C speed */
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#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
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/*
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* MII PHY configuration
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*
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*/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
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/* 32usec min. for LXT971A */
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#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
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/*
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* RTC configuration
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*
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* Note that DS1307 RTC is limited to 100Khz I2C bus.
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*
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*/
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#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
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/*
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* PCI stuff
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*
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*/
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#define CONFIG_PCI /* include pci support */
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*
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* IDE stuff
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*
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*/
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#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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/*
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* Environment configuration
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*
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*/
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#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
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#undef CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_EEPROM
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/*
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* General Memory organization
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*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_SIZE 0x02000000
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
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#if CFG_MONITOR_BASE < CFG_FLASH_BASE
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#define CFG_RAMSTART
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#endif
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#if defined(CFG_ENV_IS_IN_FLASH)
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#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
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#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
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#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
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#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
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#endif
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/*
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* FLASH Device configuration
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*
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*/
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#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
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#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
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#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
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#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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/*
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* On Chip Memory location/size
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*
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*/
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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/*
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* Global info and initial stack
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*
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*/
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*
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* Cache configuration
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*
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*/
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#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
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/* have only 8kB, 16kB is save here */
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#define CFG_CACHELINE_SIZE 32
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/*
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* Miscellaneous board specific definitions
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*
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*/
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#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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