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https://github.com/brain-hackers/u-boot-brain
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8bd5dcd895
This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Take from coreboot project file of the same name
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*/
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#ifndef _ASM_ARCH_LPC_H
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#define _ASM_ARCH_LPC_H
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#define LPC_SERIRQ_CTL 0x64
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#define LPC_SCNT_EN BIT(7)
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#define LPC_SCNT_MODE BIT(6)
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#define LPC_IO_DECODE 0x80
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#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/
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#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/
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/*
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* Use IO_<peripheral>_<IO port> style macros defined in lpc_lib.h
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* to enable decoding of I/O locations for a peripheral
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*/
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#define LPC_IO_ENABLES 0x82
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#define LPC_GENERIC_IO_RANGE(n) ((((n) & 0x3) * 4) + 0x84)
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#define LPC_LGIR_AMASK_MASK (0xfc << 16)
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#define LPC_LGIR_ADDR_MASK 0xfffc
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#define LPC_LGIR_EN BIT(0)
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#define LPC_LGIR_MAX_WINDOW_SIZE 256
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#define LPC_GENERIC_MEM_RANGE 0x98
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#define LPC_LGMR_ADDR_MASK 0xffff0000
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#define LPC_LGMR_EN BIT(0)
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#define LPC_LGMR_WINDOW_SIZE (64 * KiB)
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#define LPC_BIOS_CNTL 0xdc
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#define LPC_BC_BILD BIT(7)
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#define LPC_BC_LE BIT(1)
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#define LPC_BC_EISS BIT(5)
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#define LPC_PCCTL 0xE0 /* PCI Clock Control */
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#define LPC_PCCTL_CLKRUN_EN BIT(0)
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/*
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* IO decode enable macros are in the format IO_<peripheral>_<IO port>.
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* For example, to open ports 0x60, 0x64 for the keyboard controller,
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* use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range,
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* the port range is selectable via the IO decodes register.
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*/
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#define LPC_IOE_EC_4E_4F BIT(13)
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#define LPC_IOE_SUPERIO_2E_2F BIT(12)
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#define LPC_IOE_EC_62_66 BIT(11)
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#define LPC_IOE_KBC_60_64 BIT(10)
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#define LPC_IOE_HGE_208 BIT(9)
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#define LPC_IOE_LGE_200 BIT(8)
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#define LPC_IOE_FDD_EN BIT(3)
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#define LPC_IOE_LPT_EN BIT(2)
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#define LPC_IOE_COMB_EN BIT(1)
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#define LPC_IOE_COMA_EN BIT(0)
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#define LPC_NUM_GENERIC_IO_RANGES 4
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#define LPC_IO_ENABLES 0x82
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/**
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* lpc_enable_fixed_io_ranges() - enable the fixed I/O ranges
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*
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* @io_enables: Mask of things to enable (LPC_IOE_.)
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*/
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void lpc_enable_fixed_io_ranges(uint io_enables);
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/**
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* lpc_open_pmio_window() - Open an IO port range
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*
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* @base: Base I/O address (e.g. 0x800)
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* @size: Size of window (e.g. 0x100)
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* @return 0 if OK, -ENOSPC if there are no more windows available, -EALREADY
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* if already set up
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*/
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int lpc_open_pmio_window(uint base, uint size);
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/**
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* lpc_io_setup_comm_a_b() - Set up basic serial UARTs
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*
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* Set up the LPC to handle I/O to the COMA/COMB serial UART addresses
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* 2f8-2ff and 3f8-3ff.
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*/
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void lpc_io_setup_comm_a_b(void);
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#endif
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