mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 13:46:17 +09:00
ed50d3fae4
Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
29 lines
1.1 KiB
Makefile
29 lines
1.1 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (c) 2016, NVIDIA CORPORATION.
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#
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obj-$(CONFIG_DM_RESET) += reset-uclass.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
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obj-$(CONFIG_STI_RESET) += sti-reset.o
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obj-$(CONFIG_STM32_RESET) += stm32-reset.o
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obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
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obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
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obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
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obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
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obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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