mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
4ceb5c6db2
Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_ddr_sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DCFG_GPPORCR1 0x20
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#define GPPORCR1_MEM_MASK (0x7 << 5)
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#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5)
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#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5)
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#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5)
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#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5)
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#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5)
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#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5)
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#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5)
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static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
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.cs[0].bnds = 0x0000007f,
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.cs[0].config = 0x80044402,
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.cs[1].bnds = 0x008000ff,
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.cs[1].config = 0x80004402,
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.timing_cfg_0 = 0x9011010c,
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.timing_cfg_3 = 0x010c1000,
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.timing_cfg_1 = 0xbcb48c66,
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.timing_cfg_2 = 0x0fc0d118,
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.ddr_sdram_cfg = 0xe70c000c,
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.ddr_sdram_cfg_2 = 0x24401111,
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.ddr_sdram_mode = 0x00441c70,
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.ddr_sdram_mode_3 = 0x00001c70,
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.ddr_sdram_mode_5 = 0x00001c70,
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.ddr_sdram_mode_7 = 0x00001c70,
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.ddr_sdram_mode_2 = 0x00180000,
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.ddr_sdram_mode_4 = 0x00180000,
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.ddr_sdram_mode_6 = 0x00180000,
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.ddr_sdram_mode_8 = 0x00180000,
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.ddr_sdram_interval = 0x0c30030c,
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.ddr_data_init = 0xdeadbeef,
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.ddr_sdram_clk_cntl = 0x02400000,
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.timing_cfg_4 = 0x00000001,
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.timing_cfg_5 = 0x04401400,
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.ddr_zq_cntl = 0x89080600,
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.ddr_wrlvl_cntl = 0x8675f606,
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.ddr_wrlvl_cntl_2 = 0x04080700,
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.ddr_wrlvl_cntl_3 = 0x00000009,
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.ddr_cdr1 = 0x80040000,
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.ddr_cdr2 = 0x0000bc01,
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};
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int fsl_initdram(void)
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{
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u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
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phys_size_t dram_size;
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switch (gpporcr1 & GPPORCR1_MEM_MASK) {
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case GPPORCR1_MEM_2GB_CS0:
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dram_size = 0x80000000;
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ddr_cfg_regs.cs[1].bnds = 0;
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ddr_cfg_regs.cs[1].config = 0;
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ddr_cfg_regs.cs[1].config_2 = 0;
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break;
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case GPPORCR1_MEM_4GB_CS0_1:
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dram_size = 0x100000000ULL;
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break;
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case GPPORCR1_MEM_512MB_CS0:
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dram_size = 0x20000000;
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fallthrough; /* for now */
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case GPPORCR1_MEM_1GB_CS0:
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dram_size = 0x40000000;
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fallthrough; /* for now */
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case GPPORCR1_MEM_4GB_CS0_2:
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dram_size = 0x100000000ULL;
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fallthrough; /* for now */
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case GPPORCR1_MEM_8GB_CS0_1:
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case GPPORCR1_MEM_8GB_CS0_1_2_3:
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dram_size = 0x200000000ULL;
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fallthrough; /* for now */
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default:
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panic("Unsupported memory configuration (%08x)\n",
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gpporcr1 & GPPORCR1_MEM_MASK);
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break;
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}
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if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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gd->ram_size = dram_size;
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return 0;
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}
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