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https://github.com/brain-hackers/u-boot-brain
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![Rafal Jaworowski](/assets/img/avatar_default.png)
The following MPC5121e subsystems are supported: - low-level CPU init - NOR Boot Flash (common CFI driver) - DDR SDRAM - FEC - I2C - Watchdog Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Jan Wrobel <wrr@semihalf.com>
198 lines
4.7 KiB
C
198 lines
4.7 KiB
C
/*
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* (C) Copyright 2000 - 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Based ont the MPC5200 PSC driver.
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* Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
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*/
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/*
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* Minimal serial functions needed to use one of the PSC ports
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* as serial console interface.
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_PSC_CONSOLE)
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static void fifo_init (volatile psc512x_t *psc)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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/* reset Rx & Tx fifo slice */
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psc->rfcmd = PSC_FIFO_RESET_SLICE;
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psc->tfcmd = PSC_FIFO_RESET_SLICE;
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/* disable Tx & Rx FIFO interrupts */
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psc->rfintmask = 0;
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psc->tfintmask = 0;
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psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
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psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
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/* enable Tx & Rx FIFO slice */
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psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
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psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
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im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
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__asm__ volatile ("sync");
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}
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int serial_init(void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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unsigned long baseclk;
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int div;
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fifo_init (psc);
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/* set MR register to point to MR1 */
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psc->command = PSC_SEL_MODE_REG_1;
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/* disable Tx/Rx */
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psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
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/* choose the prescaler by 16 for the Tx/Rx clock generation */
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psc->psc_clock_select = 0xdd00;
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/* switch to UART mode */
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psc->sicr = 0;
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/* mode register points to mr1 */
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/* configure parity, bit length and so on in mode register 1*/
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psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
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/* now, mode register points to mr2 */
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psc->mode = PSC_MODE_1_STOPBIT;
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/* calculate dividor for setting PSC CTUR and CTLR registers */
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baseclk = (gd->ipb_clk + 8) / 16;
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div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
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psc->ctur = (div >> 8) & 0xff;
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/* set baudrate */
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psc->ctlr = div & 0xff;
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/* disable all interrupts */
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psc->psc_imr = 0;
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/* reset and enable Rx/Tx */
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psc->command = PSC_RST_RX;
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psc->command = PSC_RST_TX;
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psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
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return 0;
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}
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void serial_putc (const char c)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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if (c == '\n')
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serial_putc ('\r');
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/* Wait for last character to go. */
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while (!(psc->psc_status & PSC_SR_TXEMP))
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;
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psc->tfdata_8 = c;
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}
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void serial_putc_raw (const char c)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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/* Wait for last character to go. */
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while (!(psc->psc_status & PSC_SR_TXEMP))
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;
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psc->tfdata_8 = c;
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}
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void serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int serial_getc (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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/* Wait for a character to arrive. */
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while (psc->rfstat & PSC_FIFO_EMPTY)
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;
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return psc->rfdata_8;
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}
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int serial_tstc (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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return !(psc->rfstat & PSC_FIFO_EMPTY);
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}
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void serial_setbrg (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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unsigned long baseclk, div;
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baseclk = (gd->csb_clk + 8) / 16;
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div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
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psc->ctur = (div >> 8) & 0xFF;
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psc->ctlr = div & 0xff; /* set baudrate */
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}
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void serial_setrts(int s)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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if (s) {
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/* Assert RTS (become LOW) */
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psc->op1 = 0x1;
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}
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else {
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/* Negate RTS (become HIGH) */
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psc->op0 = 0x1;
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}
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}
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int serial_getcts(void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
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return (psc->ip & 0x1) ? 0 : 1;
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}
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#endif /* CONFIG_PSC_CONSOLE */
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