mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 20:38:52 +09:00
![Peter Pearse](/assets/img/avatar_default.png)
Merge to two at45.c files into a common file, split to at45.c and spi.c Fix spelling error in DM9161 PHY Support. Initialize at91rm9200 board (and set LED). Add PIO control for at91rm9200dk LEDs and Mux. Change dataflash partition boundaries to be compatible with Linux 2.6. Signed-off-by: Peter Pearse <peter.pearse@arm.com> Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
524 lines
12 KiB
ArmAsm
524 lines
12 KiB
ArmAsm
/*
|
|
* armboot - Startup Code for ARM920 CPU-core
|
|
*
|
|
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
|
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
|
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
|
|
#include <config.h>
|
|
#include <version.h>
|
|
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
|
|
#include <led.h>
|
|
#endif
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* Jump vector table as in table 3.1 in [1]
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
|
|
.globl _start
|
|
_start: b reset
|
|
ldr pc, _undefined_instruction
|
|
ldr pc, _software_interrupt
|
|
ldr pc, _prefetch_abort
|
|
ldr pc, _data_abort
|
|
ldr pc, _not_used
|
|
ldr pc, _irq
|
|
ldr pc, _fiq
|
|
|
|
_undefined_instruction: .word undefined_instruction
|
|
_software_interrupt: .word software_interrupt
|
|
_prefetch_abort: .word prefetch_abort
|
|
_data_abort: .word data_abort
|
|
_not_used: .word not_used
|
|
_irq: .word irq
|
|
_fiq: .word fiq
|
|
|
|
.balignl 16,0xdeadbeef
|
|
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* Startup Code (reset vector)
|
|
*
|
|
* do important init only if we don't start from memory!
|
|
* relocate armboot to ram
|
|
* setup stack
|
|
* jump to second stage
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
_TEXT_BASE:
|
|
.word TEXT_BASE
|
|
|
|
.globl _armboot_start
|
|
_armboot_start:
|
|
.word _start
|
|
|
|
/*
|
|
* These are defined in the board-specific linker script.
|
|
*/
|
|
.globl _bss_start
|
|
_bss_start:
|
|
.word __bss_start
|
|
|
|
.globl _bss_end
|
|
_bss_end:
|
|
.word _end
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
/* IRQ stack memory (calculated at run-time) */
|
|
.globl IRQ_STACK_START
|
|
IRQ_STACK_START:
|
|
.word 0x0badc0de
|
|
|
|
/* IRQ stack memory (calculated at run-time) */
|
|
.globl FIQ_STACK_START
|
|
FIQ_STACK_START:
|
|
.word 0x0badc0de
|
|
#endif
|
|
|
|
|
|
/*
|
|
* the actual reset code
|
|
*/
|
|
|
|
reset:
|
|
/*
|
|
* set the cpu to SVC32 mode
|
|
*/
|
|
mrs r0,cpsr
|
|
bic r0,r0,#0x1f
|
|
orr r0,r0,#0xd3
|
|
msr cpsr,r0
|
|
|
|
#if CONFIG_AT91RM9200
|
|
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
|
|
bl LED_init
|
|
bl red_LED_on
|
|
#endif
|
|
|
|
#ifdef CONFIG_BOOTBINFUNC
|
|
/* code based on entry.S from ATMEL */
|
|
#define AT91C_BASE_CKGR 0xFFFFFC20
|
|
#define CKGR_MOR 0
|
|
/* Get the CKGR Base Address */
|
|
ldr r1, =AT91C_BASE_CKGR
|
|
|
|
/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
|
|
/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
|
|
ldr r0, =0x0000FF01
|
|
str r0, [r1, #CKGR_MOR]
|
|
/* Add loop to compensate Main Oscillator startup time */
|
|
ldr r0, =0x00000010
|
|
LoopOsc:
|
|
subs r0, r0, #1
|
|
bhi LoopOsc
|
|
/* scratch stack */
|
|
ldr r1, =0x00204000
|
|
/* Insure word alignment */
|
|
bic r1, r1, #3
|
|
/* Init stack SYS */
|
|
mov sp, r1
|
|
/*
|
|
* This does a lot more than just set up the memory, which
|
|
* is why it's called lowlevelinit
|
|
*/
|
|
bl lowlevelinit /* in memsetup.S */
|
|
bl icache_enable;
|
|
/* ------------------------------------
|
|
* Read/modify/write CP15 control register
|
|
* -------------------------------------
|
|
* read cp15 control register (cp15 r1) in r0
|
|
* ------------------------------------
|
|
*/
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
/* Reset bit :Little Endian end fast bus mode */
|
|
ldr r3, =0xC0000080
|
|
/* Set bit :Asynchronous clock mode, Not Fast Bus */
|
|
ldr r4, =0xC0000000
|
|
bic r0, r0, r3
|
|
orr r0, r0, r4
|
|
/* write r0 in cp15 control register (cp15 r1) */
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
#endif /* CONFIG_BOOTBINFUNC */
|
|
/*
|
|
* relocate exeception table
|
|
*/
|
|
ldr r0, =_start
|
|
ldr r1, =0x0
|
|
mov r2, #16
|
|
copyex:
|
|
subs r2, r2, #1
|
|
ldr r3, [r0], #4
|
|
str r3, [r1], #4
|
|
bne copyex
|
|
#endif
|
|
|
|
/* turn off the watchdog */
|
|
#if defined(CONFIG_S3C2400)
|
|
# define pWTCON 0x15300000
|
|
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
|
# define CLKDIVN 0x14800014 /* clock divisor register */
|
|
#elif defined(CONFIG_S3C2410)
|
|
# define pWTCON 0x53000000
|
|
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
|
# define INTSUBMSK 0x4A00001C
|
|
# define CLKDIVN 0x4C000014 /* clock divisor register */
|
|
#endif
|
|
|
|
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
|
|
ldr r0, =pWTCON
|
|
mov r1, #0x0
|
|
str r1, [r0]
|
|
|
|
/*
|
|
* mask all IRQs by setting all bits in the INTMR - default
|
|
*/
|
|
mov r1, #0xffffffff
|
|
ldr r0, =INTMSK
|
|
str r1, [r0]
|
|
# if defined(CONFIG_S3C2410)
|
|
ldr r1, =0x3ff
|
|
ldr r0, =INTSUBMSK
|
|
str r1, [r0]
|
|
# endif
|
|
|
|
/* FCLK:HCLK:PCLK = 1:2:4 */
|
|
/* default FCLK is 120 MHz ! */
|
|
ldr r0, =CLKDIVN
|
|
mov r1, #3
|
|
str r1, [r0]
|
|
#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
|
|
|
|
/*
|
|
* we do sys-critical inits only at reboot,
|
|
* not when booting from ram!
|
|
*/
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
bl cpu_init_crit
|
|
#endif
|
|
|
|
#ifdef CONFIG_AT91RM9200
|
|
#ifdef CONFIG_BOOTBINFUNC
|
|
relocate: /* relocate U-Boot to RAM */
|
|
adr r0, _start /* r0 <- current position of code */
|
|
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
|
cmp r0, r1 /* don't reloc during debug */
|
|
beq stack_setup
|
|
|
|
ldr r2, _armboot_start
|
|
ldr r3, _bss_start
|
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
|
add r2, r0, r2 /* r2 <- source end address */
|
|
|
|
copy_loop:
|
|
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
|
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
|
cmp r0, r2 /* until source end addreee [r2] */
|
|
ble copy_loop
|
|
#endif /* CONFIG_BOOTBINFUNC */
|
|
#else
|
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
|
relocate: /* relocate U-Boot to RAM */
|
|
adr r0, _start /* r0 <- current position of code */
|
|
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
|
cmp r0, r1 /* don't reloc during debug */
|
|
beq stack_setup
|
|
|
|
ldr r2, _armboot_start
|
|
ldr r3, _bss_start
|
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
|
add r2, r0, r2 /* r2 <- source end address */
|
|
|
|
copy_loop:
|
|
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
|
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
|
cmp r0, r2 /* until source end addreee [r2] */
|
|
ble copy_loop
|
|
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
|
|
#endif
|
|
/* Set up the stack */
|
|
stack_setup:
|
|
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
|
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
|
|
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
|
|
#ifdef CONFIG_USE_IRQ
|
|
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
|
#endif
|
|
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
|
|
|
clear_bss:
|
|
ldr r0, _bss_start /* find start of bss segment */
|
|
ldr r1, _bss_end /* stop here */
|
|
mov r2, #0x00000000 /* clear */
|
|
|
|
clbss_l:str r2, [r0] /* clear loop... */
|
|
add r0, r0, #4
|
|
cmp r0, r1
|
|
ble clbss_l
|
|
|
|
#if 0
|
|
/* try doing this stuff after the relocation */
|
|
ldr r0, =pWTCON
|
|
mov r1, #0x0
|
|
str r1, [r0]
|
|
|
|
/*
|
|
* mask all IRQs by setting all bits in the INTMR - default
|
|
*/
|
|
mov r1, #0xffffffff
|
|
ldr r0, =INTMR
|
|
str r1, [r0]
|
|
|
|
/* FCLK:HCLK:PCLK = 1:2:4 */
|
|
/* default FCLK is 120 MHz ! */
|
|
ldr r0, =CLKDIVN
|
|
mov r1, #3
|
|
str r1, [r0]
|
|
/* END stuff after relocation */
|
|
#endif
|
|
|
|
ldr pc, _start_armboot
|
|
|
|
_start_armboot: .word start_armboot
|
|
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* CPU_init_critical registers
|
|
*
|
|
* setup important registers
|
|
* setup memory timing
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
cpu_init_crit:
|
|
/*
|
|
* flush v4 I/D caches
|
|
*/
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
|
|
|
/*
|
|
* disable MMU stuff and caches
|
|
*/
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
|
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
|
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
|
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
|
|
/*
|
|
* before relocating, we have to setup RAM timing
|
|
* because memory timing is board-dependend, you will
|
|
* find a lowlevel_init.S in your board directory.
|
|
*/
|
|
mov ip, lr
|
|
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
|
|
|
|
#else
|
|
bl lowlevel_init
|
|
#endif
|
|
mov lr, ip
|
|
mov pc, lr
|
|
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* Interrupt handling
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
@
|
|
@ IRQ stack frame.
|
|
@
|
|
#define S_FRAME_SIZE 72
|
|
|
|
#define S_OLD_R0 68
|
|
#define S_PSR 64
|
|
#define S_PC 60
|
|
#define S_LR 56
|
|
#define S_SP 52
|
|
|
|
#define S_IP 48
|
|
#define S_FP 44
|
|
#define S_R10 40
|
|
#define S_R9 36
|
|
#define S_R8 32
|
|
#define S_R7 28
|
|
#define S_R6 24
|
|
#define S_R5 20
|
|
#define S_R4 16
|
|
#define S_R3 12
|
|
#define S_R2 8
|
|
#define S_R1 4
|
|
#define S_R0 0
|
|
|
|
#define MODE_SVC 0x13
|
|
#define I_BIT 0x80
|
|
|
|
/*
|
|
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
|
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
|
|
*/
|
|
|
|
.macro bad_save_user_regs
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
|
ldr r2, _armboot_start
|
|
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
|
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
|
ldmia r2, {r2 - r3} @ get pc, cpsr
|
|
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
|
|
|
add r5, sp, #S_SP
|
|
mov r1, lr
|
|
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
|
mov r0, sp
|
|
.endm
|
|
|
|
.macro irq_save_user_regs
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
|
add r8, sp, #S_PC
|
|
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
|
str lr, [r8, #0] @ Save calling PC
|
|
mrs r6, spsr
|
|
str r6, [r8, #4] @ Save CPSR
|
|
str r0, [r8, #8] @ Save OLD_R0
|
|
mov r0, sp
|
|
.endm
|
|
|
|
.macro irq_restore_user_regs
|
|
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
|
mov r0, r0
|
|
ldr lr, [sp, #S_PC] @ Get PC
|
|
add sp, sp, #S_FRAME_SIZE
|
|
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
|
.endm
|
|
|
|
.macro get_bad_stack
|
|
ldr r13, _armboot_start @ setup our mode stack
|
|
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
|
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
|
|
|
str lr, [r13] @ save caller lr / spsr
|
|
mrs lr, spsr
|
|
str lr, [r13, #4]
|
|
|
|
mov r13, #MODE_SVC @ prepare SVC-Mode
|
|
@ msr spsr_c, r13
|
|
msr spsr, r13
|
|
mov lr, pc
|
|
movs pc, lr
|
|
.endm
|
|
|
|
.macro get_irq_stack @ setup IRQ stack
|
|
ldr sp, IRQ_STACK_START
|
|
.endm
|
|
|
|
.macro get_fiq_stack @ setup FIQ stack
|
|
ldr sp, FIQ_STACK_START
|
|
.endm
|
|
|
|
/*
|
|
* exception handlers
|
|
*/
|
|
.align 5
|
|
undefined_instruction:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_undefined_instruction
|
|
|
|
.align 5
|
|
software_interrupt:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_software_interrupt
|
|
|
|
.align 5
|
|
prefetch_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_prefetch_abort
|
|
|
|
.align 5
|
|
data_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_data_abort
|
|
|
|
.align 5
|
|
not_used:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_not_used
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
.align 5
|
|
irq:
|
|
get_irq_stack
|
|
irq_save_user_regs
|
|
bl do_irq
|
|
irq_restore_user_regs
|
|
|
|
.align 5
|
|
fiq:
|
|
get_fiq_stack
|
|
/* someone ought to write a more effiction fiq_save_user_regs */
|
|
irq_save_user_regs
|
|
bl do_fiq
|
|
irq_restore_user_regs
|
|
|
|
#else
|
|
|
|
.align 5
|
|
irq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_irq
|
|
|
|
.align 5
|
|
fiq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_fiq
|
|
|
|
#endif
|