mirror of
https://github.com/brain-hackers/u-boot-brain
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753 lines
20 KiB
C
753 lines
20 KiB
C
/*
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* (C) Copyright 2004, Freescale, Inc
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* TsiChung Liew, Tsi-Chung.Liew@freescale.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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DESCRIPTION
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Read Dram spd and base on its information to calculate the memory size,
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characteristics to initialize the dram on MPC8220
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*/
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#include <common.h>
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#include <mpc8220.h>
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#include "i2cCore.h"
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#include "dramSetup.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define SPD_SIZE CFG_SDRAM_SPD_SIZE
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#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
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#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS
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int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
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{
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int i;
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for (i = 0; i < I2C_POLL_COUNT; i++) {
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if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0))
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return (OK);
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}
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return (ERROR);
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}
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int spd_clear (volatile i2c8220_t * pi2c)
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{
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pi2c->adr = 0;
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pi2c->fdr = 0;
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pi2c->cr = 0;
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pi2c->sr = 0;
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return (OK);
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}
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int spd_stop (volatile i2c8220_t * pi2c)
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{
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pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */
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if (spd_status (pi2c, I2C_STA_BB, 0) != OK)
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return ERROR;
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return (OK);
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}
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int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
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{
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pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */
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*readb = pi2c->dr; /* Read a byte */
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/*
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Set I2C_CTRL_TXAK will cause Transfer pending and
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set I2C_CTRL_STA will cause Interrupt pending
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*/
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if (*index != 2) {
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if (spd_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */
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return ERROR;
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}
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if (*index != 1) {
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if (spd_status (pi2c, I2C_STA_IF, 1) != OK)
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return ERROR;
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}
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return (OK);
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}
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int readSpdData (u8 * spdData)
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{
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volatile i2c8220_t *pi2cReg;
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volatile pcfg8220_t *pcfg;
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u8 slvAdr = DRAM_SPD;
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u8 Tmp;
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int Length = SPD_SIZE;
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int i = 0;
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/* Enable Port Configuration for SDA and SDL signals */
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pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
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__asm__ ("sync");
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pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG;
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__asm__ ("sync");
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/* Points the structure to I2c mbar memory offset */
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pi2cReg = (volatile i2c8220_t *) (MMAP_I2C);
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/* Clear FDR, ADR, SR and CR reg */
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pi2cReg->adr = 0;
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pi2cReg->fdr = 0;
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pi2cReg->cr = 0;
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pi2cReg->sr = 0;
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/* Set for fix XLB Bus Frequency */
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switch (gd->bus_clk) {
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case 60000000:
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pi2cReg->fdr = 0x15;
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break;
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case 70000000:
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pi2cReg->fdr = 0x16;
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break;
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case 80000000:
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pi2cReg->fdr = 0x3a;
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break;
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case 90000000:
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pi2cReg->fdr = 0x17;
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break;
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case 100000000:
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pi2cReg->fdr = 0x3b;
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break;
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case 110000000:
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pi2cReg->fdr = 0x18;
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break;
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case 120000000:
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pi2cReg->fdr = 0x19;
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break;
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case 130000000:
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pi2cReg->fdr = 0x1a;
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break;
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}
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pi2cReg->adr = CFG_I2C_SLAVE<<1;
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pi2cReg->cr = I2C_CTL_EN; /* Set Enable */
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/*
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The I2C bus should be in Idle state. If the bus is busy,
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clear the STA bit in control register
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*/
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if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) {
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if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA)
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pi2cReg->cr &= ~I2C_CTL_STA;
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/* Check again if it is still busy, return error if found */
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if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK)
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return ERROR;
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}
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pi2cReg->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */
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pi2cReg->cr |= I2C_CTL_STA; /* Generate start signal */
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if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK)
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return ERROR;
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/* Write slave address */
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pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
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pi2cReg->dr = slvAdr; /* Write a byte */
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if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
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spd_stop (pi2cReg);
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return ERROR;
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}
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if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
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spd_stop (pi2cReg);
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return ERROR;
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}
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/* Issue the offset to start */
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pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
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pi2cReg->dr = 0; /* Write a byte */
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if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
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spd_stop (pi2cReg);
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return ERROR;
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}
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if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
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spd_stop (pi2cReg);
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return ERROR;
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}
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/* Set repeat start */
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pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */
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pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
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pi2cReg->dr = slvAdr | 1; /* Write a byte */
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if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
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spd_stop (pi2cReg);
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return ERROR;
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}
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if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
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spd_stop (pi2cReg);
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return ERROR;
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}
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if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
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return ERROR;
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pi2cReg->cr &= ~I2C_CTL_TX; /* Set receive mode */
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if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
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return ERROR;
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/* Dummy Read */
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if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) {
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spd_stop (pi2cReg);
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return ERROR;
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}
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i = 0;
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while (Length) {
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if (Length == 2)
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pi2cReg->cr |= I2C_CTL_TXAK;
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if (Length == 1)
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pi2cReg->cr &= ~I2C_CTL_STA;
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if (spd_readbyte (pi2cReg, spdData, &Length) != OK) {
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return spd_stop (pi2cReg);
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}
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i++;
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Length--;
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spdData++;
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}
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/* Stop the service */
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spd_stop (pi2cReg);
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return OK;
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}
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int getBankInfo (int bank, draminfo_t * pBank)
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{
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int status;
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int checksum;
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int count;
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u8 spdData[SPD_SIZE];
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if (bank > 2 || pBank == 0) {
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/* illegal values */
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return (-42);
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}
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status = readSpdData (&spdData[0]);
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if (status < 0)
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return (-1);
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/* check the checksum */
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for (count = 0, checksum = 0; count < LOC_CHECKSUM; count++)
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checksum += spdData[count];
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checksum = checksum - ((checksum / 256) * 256);
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if (checksum != spdData[LOC_CHECKSUM])
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return (-2);
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/* Get the memory type */
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if (!
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((spdData[LOC_TYPE] == TYPE_DDR)
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|| (spdData[LOC_TYPE] == TYPE_SDR)))
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/* not one of the types we support */
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return (-3);
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pBank->type = spdData[LOC_TYPE];
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/* Set logical banks */
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pBank->banks = spdData[LOC_LOGICAL_BANKS];
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/* Check that we have enough physical banks to cover the bank we are
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* figuring out. Odd-numbered banks correspond to the second bank
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* on the device.
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*/
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if (bank & 1) {
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/* Second bank of a "device" */
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if (spdData[LOC_PHYS_BANKS] < 2)
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/* this bank doesn't exist on the "device" */
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return (-4);
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if (spdData[LOC_ROWS] & 0xf0)
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/* Two asymmetric banks */
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pBank->rows = spdData[LOC_ROWS] >> 4;
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else
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pBank->rows = spdData[LOC_ROWS];
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if (spdData[LOC_COLS] & 0xf0)
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/* Two asymmetric banks */
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pBank->cols = spdData[LOC_COLS] >> 4;
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else
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pBank->cols = spdData[LOC_COLS];
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} else {
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/* First bank of a "device" */
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pBank->rows = spdData[LOC_ROWS];
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pBank->cols = spdData[LOC_COLS];
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}
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pBank->width = spdData[LOC_WIDTH_HIGH] << 8 | spdData[LOC_WIDTH_LOW];
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pBank->bursts = spdData[LOC_BURSTS];
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pBank->CAS = spdData[LOC_CAS];
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pBank->CS = spdData[LOC_CS];
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pBank->WE = spdData[LOC_WE];
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pBank->Trp = spdData[LOC_Trp];
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pBank->Trcd = spdData[LOC_Trcd];
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pBank->buffered = spdData[LOC_Buffered] & 1;
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pBank->refresh = spdData[LOC_REFRESH];
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return (0);
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}
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/* checkMuxSetting -- given a row/column device geometry, return a mask
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* of the valid DRAM controller addr_mux settings for
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* that geometry.
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*
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* Arguments: u8 rows: number of row addresses in this device
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* u8 columns: number of column addresses in this device
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*
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* Returns: a mask of the allowed addr_mux settings for this
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* geometry. Each bit in the mask represents a
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* possible addr_mux settings (for example, the
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* (1<<2) bit in the mask represents the 0b10 setting)/
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*
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*/
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u8 checkMuxSetting (u8 rows, u8 columns)
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{
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muxdesc_t *pIdx, *pMux;
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u8 mask;
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int lrows, lcolumns;
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u32 mux[4] = { 0x00080c04, 0x01080d03, 0x02080e02, 0xffffffff };
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/* Setup MuxDescriptor in SRAM space */
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/* MUXDESC AddressRuns [] = {
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{ 0, 8, 12, 4 }, / setting, columns, rows, extra columns /
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{ 1, 8, 13, 3 }, / setting, columns, rows, extra columns /
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{ 2, 8, 14, 2 }, / setting, columns, rows, extra columns /
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{ 0xff } / list terminator /
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}; */
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pIdx = (muxdesc_t *) & mux[0];
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/* Check rows x columns against each possible address mux setting */
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for (pMux = pIdx, mask = 0;; pMux++) {
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lrows = rows;
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lcolumns = columns;
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if (pMux->MuxValue == 0xff)
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break; /* end of list */
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/* For a given mux setting, since we want all the memory in a
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* device to be contiguous, we want the device "use up" the
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* address lines such that there are no extra column or row
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* address lines on the device.
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*/
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lcolumns -= pMux->Columns;
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if (lcolumns < 0)
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/* Not enough columns to get to the rows */
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continue;
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lrows -= pMux->Rows;
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if (lrows > 0)
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/* we have extra rows left -- can't do that! */
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continue;
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/* At this point, we either have to have used up all the
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* rows or we have to have no columns left.
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*/
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if (lcolumns != 0 && lrows != 0)
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/* rows AND columns are left. Bad! */
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continue;
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lcolumns -= pMux->MoreColumns;
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if (lcolumns <= 0)
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mask |= (1 << pMux->MuxValue);
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}
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return (mask);
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}
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u32 dramSetup (void)
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{
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draminfo_t DramInfo[TOTAL_BANK];
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draminfo_t *pDramInfo;
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u32 size, temp, cfg_value, mode_value, refresh;
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u8 *ptr;
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u8 bursts, Trp, Trcd, type, buffered;
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u8 muxmask, rows, columns;
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int count, banknum;
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u32 *prefresh, *pIdx;
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u32 refrate[8] = { 15625, 3900, 7800, 31300,
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62500, 125000, 0xffffffff, 0xffffffff
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};
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volatile sysconf8220_t *sysconf;
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volatile memctl8220_t *memctl;
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sysconf = (volatile sysconf8220_t *) MMAP_MBAR;
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memctl = (volatile memctl8220_t *) MMAP_MEMCTL;
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/* Set everything in the descriptions to zero */
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ptr = (u8 *) & DramInfo[0];
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for (count = 0; count < sizeof (DramInfo); count++)
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*ptr++ = 0;
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for (banknum = 0; banknum < TOTAL_BANK; banknum++)
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sysconf->cscfg[banknum];
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/* Descriptions of row/column address muxing for various
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* addr_mux settings.
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*/
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pIdx = prefresh = (u32 *) & refrate[0];
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/* Get all the info for all three logical banks */
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bursts = 0xff;
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Trp = 0;
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Trcd = 0;
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type = 0;
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buffered = 0xff;
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refresh = 0xffffffff;
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muxmask = 0xff;
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/* Two bank, CS0 and CS1 */
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for (banknum = 0, pDramInfo = &DramInfo[0];
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banknum < TOTAL_BANK; banknum++, pDramInfo++) {
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pDramInfo->ordinal = banknum; /* initial sorting */
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if (getBankInfo (banknum, pDramInfo) < 0)
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continue;
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/* get cumulative parameters of all three banks */
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if (type && pDramInfo->type != type)
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return 0;
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type = pDramInfo->type;
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rows = pDramInfo->rows;
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columns = pDramInfo->cols;
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/* This chip only supports 13 DRAM memory lines, but some devices
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* have 14 rows. To deal with this, ignore the 14th address line
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* by limiting the number of rows (and columns) to 13. This will
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* mean that for 14-row devices we will only be able to use
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* half of the memory, but it's better than nothing.
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*/
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if (rows > 13)
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rows = 13;
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if (columns > 13)
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columns = 13;
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pDramInfo->size =
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((1 << (rows + columns)) * pDramInfo->width);
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pDramInfo->size *= pDramInfo->banks;
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pDramInfo->size >>= 3;
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/* figure out which addr_mux configurations will support this device */
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muxmask &= checkMuxSetting (rows, columns);
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if (muxmask == 0)
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return 0;
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buffered = pDramInfo->buffered;
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bursts &= pDramInfo->bursts; /* union of all bursts */
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if (pDramInfo->Trp > Trp) /* worst case (longest) Trp */
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Trp = pDramInfo->Trp;
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if (pDramInfo->Trcd > Trcd) /* worst case (longest) Trcd */
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Trcd = pDramInfo->Trcd;
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prefresh = pIdx;
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/* worst case (shortest) Refresh period */
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if (refresh > prefresh[pDramInfo->refresh & 7])
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refresh = prefresh[pDramInfo->refresh & 7];
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} /* for loop */
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/* We only allow a burst length of 8! */
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if (!(bursts & 8))
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bursts = 8;
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/* Sort the devices. In order to get each chip select region
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* aligned properly, put the biggest device at the lowest address.
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* A simple bubble sort will do the trick.
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*/
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for (banknum = 0, pDramInfo = &DramInfo[0];
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banknum < TOTAL_BANK; banknum++, pDramInfo++) {
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int i;
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for (i = 0; i < TOTAL_BANK; i++) {
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if (pDramInfo->size < DramInfo[i].size &&
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pDramInfo->ordinal < DramInfo[i].ordinal) {
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/* If the current bank is smaller, but if the ordinal is also
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* smaller, swap the ordinals
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*/
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u8 temp8;
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temp8 = DramInfo[i].ordinal;
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DramInfo[i].ordinal = pDramInfo->ordinal;
|
|
pDramInfo->ordinal = temp8;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* Now figure out the base address for each bank. While
|
|
* we're at it, figure out how much memory there is.
|
|
*
|
|
*/
|
|
size = 0;
|
|
for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
|
|
int i;
|
|
|
|
for (i = 0; i < TOTAL_BANK; i++) {
|
|
if (DramInfo[i].ordinal == banknum
|
|
&& DramInfo[i].size != 0) {
|
|
DramInfo[i].base = size;
|
|
size += DramInfo[i].size;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set up the Drive Strength register */
|
|
sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH;
|
|
|
|
/* ********************** Cfg 1 ************************* */
|
|
|
|
/* Set the single read to read/write/precharge delay */
|
|
cfg_value = CFG1_SRD2RWP ((type == TYPE_DDR) ? 7 : 0xb);
|
|
|
|
/* Set the single write to read/write/precharge delay.
|
|
* This may or may not be correct. The controller spec
|
|
* says "tWR", but "tWR" does not appear in the SPD. It
|
|
* always seems to be 15nsec for the class of device we're
|
|
* using, which turns out to be 2 clock cycles at 133MHz,
|
|
* so that's what we're going to use.
|
|
*
|
|
* HOWEVER, because of a bug in the controller, for DDR
|
|
* we need to set this to be the same as the value
|
|
* calculated for bwt2rwp.
|
|
*/
|
|
cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2);
|
|
|
|
/* Set the Read CAS latency. We're going to use a CL of
|
|
* 2.5 for DDR and 2 SDR.
|
|
*/
|
|
cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2);
|
|
|
|
|
|
/* Set the Active to Read/Write delay. This depends
|
|
* on Trcd which is reported as nanoseconds times 4.
|
|
* We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz)
|
|
* which gives us a dimensionless quantity. Play games with
|
|
* the divisions so we don't run out of dynamic ranges.
|
|
*/
|
|
/* account for megaherz and the times 4 */
|
|
temp = (Trcd * (gd->bus_clk / 1000000)) / 4;
|
|
|
|
/* account for nanoseconds and round up, with a minimum value of 2 */
|
|
temp = ((temp + 999) / 1000) - 1;
|
|
if (temp < 2)
|
|
temp = 2;
|
|
|
|
cfg_value |= CFG1_ACT2WR (temp);
|
|
|
|
/* Set the precharge to active delay. This depends
|
|
* on Trp which is reported as nanoseconds times 4.
|
|
* We want to calculate Trp (in nanoseconds) times XLB clock (in Hz)
|
|
* which gives us a dimensionless quantity. Play games with
|
|
* the divisions so we don't run out of dynamic ranges.
|
|
*/
|
|
/* account for megaherz and the times 4 */
|
|
temp = (Trp * (gd->bus_clk / 1000000)) / 4;
|
|
|
|
/* account for nanoseconds and round up, then subtract 1, with a
|
|
* minumum value of 1 and a maximum value of 7.
|
|
*/
|
|
temp = (((temp + 999) / 1000) - 1) & 7;
|
|
if (temp < 1)
|
|
temp = 1;
|
|
|
|
cfg_value |= CFG1_PRE2ACT (temp);
|
|
|
|
/* Set refresh to active delay. This depends
|
|
* on Trfc which is not reported in the SPD.
|
|
* We'll use a nominal value of 75nsec which is
|
|
* what the controller spec uses.
|
|
*/
|
|
temp = (75 * (gd->bus_clk / 1000000));
|
|
/* account for nanoseconds and round up, then subtract 1 */
|
|
cfg_value |= CFG1_REF2ACT (((temp + 999) / 1000) - 1);
|
|
|
|
/* Set the write latency, using the values given in the controller spec */
|
|
cfg_value |= CFG1_WLATENCY ((type == TYPE_DDR) ? 3 : 0);
|
|
memctl->cfg1 = cfg_value; /* cfg 1 */
|
|
asm volatile ("sync");
|
|
|
|
|
|
/* ********************** Cfg 2 ************************* */
|
|
|
|
/* Set the burst read to read/precharge delay */
|
|
cfg_value = CFG2_BRD2RP ((type == TYPE_DDR) ? 5 : 8);
|
|
|
|
/* Set the burst write to read/precharge delay. Semi-magic numbers
|
|
* based on the controller spec recommendations, assuming tWR is
|
|
* two clock cycles.
|
|
*/
|
|
cfg_value |= CFG2_BWT2RWP ((type == TYPE_DDR) ? 7 : 10);
|
|
|
|
/* Set the Burst read to write delay. Semi-magic numbers
|
|
* based on the DRAM controller documentation.
|
|
*/
|
|
cfg_value |= CFG2_BRD2WT ((type == TYPE_DDR) ? 7 : 0xb);
|
|
|
|
/* Set the burst length -- must be 8!! Well, 7, actually, becuase
|
|
* it's burst lenght minus 1.
|
|
*/
|
|
cfg_value |= CFG2_BURSTLEN (7);
|
|
memctl->cfg2 = cfg_value; /* cfg 2 */
|
|
asm volatile ("sync");
|
|
|
|
|
|
/* ********************** mode ************************* */
|
|
|
|
/* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit,
|
|
* disable automatic refresh.
|
|
*/
|
|
cfg_value = CTL_MODE_ENABLE | CTL_CKE_HIGH |
|
|
((type == TYPE_DDR) ? CTL_DDR_MODE : 0);
|
|
|
|
/* Set the address mux based on whichever setting(s) is/are common
|
|
* to all the devices we have. If there is more than one, choose
|
|
* one arbitrarily.
|
|
*/
|
|
if (muxmask & 0x4)
|
|
cfg_value |= CTL_ADDRMUX (2);
|
|
else if (muxmask & 0x2)
|
|
cfg_value |= CTL_ADDRMUX (1);
|
|
else
|
|
cfg_value |= CTL_ADDRMUX (0);
|
|
|
|
/* Set the refresh interval. */
|
|
temp = ((refresh * (gd->bus_clk / 1000000)) / (1000 * 64)) - 1;
|
|
cfg_value |= CTL_REFRESH_INTERVAL (temp);
|
|
|
|
/* Set buffered/non-buffered memory */
|
|
if (buffered)
|
|
cfg_value |= CTL_BUFFERED;
|
|
|
|
memctl->ctrl = cfg_value; /* ctrl */
|
|
asm volatile ("sync");
|
|
|
|
if (type == TYPE_DDR) {
|
|
/* issue precharge all */
|
|
temp = cfg_value | CTL_PRECHARGE_CMD;
|
|
memctl->ctrl = temp; /* ctrl */
|
|
asm volatile ("sync");
|
|
}
|
|
|
|
|
|
/* Set up mode value for CAS latency */
|
|
#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
|
|
mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
|
|
MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
|
|
#else
|
|
mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
|
|
MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD);
|
|
#endif
|
|
asm volatile ("sync");
|
|
|
|
/* Write Extended Mode - enable DLL */
|
|
if (type == TYPE_DDR) {
|
|
temp = MODE_EXTENDED | MODE_X_DLL_ENABLE |
|
|
MODE_X_DS_NORMAL | MODE_CMD;
|
|
memctl->mode = (temp >> 16); /* mode */
|
|
asm volatile ("sync");
|
|
|
|
/* Write Mode - reset DLL, set CAS latency */
|
|
temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL);
|
|
memctl->mode = (temp >> 16); /* mode */
|
|
asm volatile ("sync");
|
|
}
|
|
|
|
/* Program the chip selects. */
|
|
for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
|
|
if (DramInfo[banknum].size != 0) {
|
|
u32 mask;
|
|
int i;
|
|
|
|
for (i = 0, mask = 1; i < 32; mask <<= 1, i++) {
|
|
if (DramInfo[banknum].size & mask)
|
|
break;
|
|
}
|
|
temp = (DramInfo[banknum].base & 0xfff00000) | (i -
|
|
1);
|
|
|
|
sysconf->cscfg[banknum] = temp;
|
|
asm volatile ("sync");
|
|
}
|
|
}
|
|
|
|
/* Wait for DLL lock */
|
|
udelay (200);
|
|
|
|
temp = cfg_value | CTL_PRECHARGE_CMD; /* issue precharge all */
|
|
memctl->ctrl = temp; /* ctrl */
|
|
asm volatile ("sync");
|
|
|
|
temp = cfg_value | CTL_REFRESH_CMD; /* issue precharge all */
|
|
memctl->ctrl = temp; /* ctrl */
|
|
asm volatile ("sync");
|
|
|
|
memctl->ctrl = temp; /* ctrl */
|
|
asm volatile ("sync");
|
|
|
|
/* Write Mode - DLL normal */
|
|
temp = mode_value | MODE_OPMODE (MODE_OPMODE_NORMAL);
|
|
memctl->mode = (temp >> 16); /* mode */
|
|
asm volatile ("sync");
|
|
|
|
/* Enable refresh, enable DQS's (if DDR), and lock the control register */
|
|
cfg_value &= ~CTL_MODE_ENABLE; /* lock register */
|
|
cfg_value |= CTL_REFRESH_ENABLE; /* enable refresh */
|
|
|
|
if (type == TYPE_DDR)
|
|
cfg_value |= CTL_DQSOEN (0xf); /* enable DQS's for DDR */
|
|
|
|
memctl->ctrl = cfg_value; /* ctrl */
|
|
asm volatile ("sync");
|
|
|
|
return size;
|
|
}
|