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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-11 07:13:21 +09:00
![Hans de Goede](/assets/img/avatar_default.png)
The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
377 lines
9.1 KiB
C
377 lines
9.1 KiB
C
/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Aaron <leafy.myeh@allwinnertech.com>
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*
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* MMC driver for allwinner sunxi platform.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mmc.h>
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struct sunxi_mmc_host {
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unsigned mmc_no;
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uint32_t *mclkreg;
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unsigned database;
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unsigned fatal_err;
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unsigned mod_clk;
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struct sunxi_mmc *reg;
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struct mmc_config cfg;
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};
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/* support 4 mmc hosts */
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struct sunxi_mmc_host mmc_host[4];
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static int mmc_resource_init(int sdc_no)
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{
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struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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debug("init mmc %d resource\n", sdc_no);
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switch (sdc_no) {
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case 0:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
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mmchost->mclkreg = &ccm->sd0_clk_cfg;
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break;
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case 1:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
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mmchost->mclkreg = &ccm->sd1_clk_cfg;
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break;
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case 2:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
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mmchost->mclkreg = &ccm->sd2_clk_cfg;
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break;
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case 3:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
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mmchost->mclkreg = &ccm->sd3_clk_cfg;
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break;
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default:
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printf("Wrong mmc number %d\n", sdc_no);
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return -1;
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}
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mmchost->database = (unsigned int)mmchost->reg + 0x100;
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mmchost->mmc_no = sdc_no;
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return 0;
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}
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static int mmc_clk_io_on(int sdc_no)
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{
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unsigned int pll_clk;
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unsigned int divider;
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struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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debug("init mmc %d clock and io\n", sdc_no);
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/* config ahb clock */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
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/* config mod clock */
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pll_clk = clock_get_pll6();
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/* should be close to 100 MHz but no more, so round up */
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divider = ((pll_clk + 99999999) / 100000000) - 1;
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writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
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mmchost->mclkreg);
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mmchost->mod_clk = pll_clk / (divider + 1);
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return 0;
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}
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static int mmc_update_clk(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int cmd;
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unsigned timeout_msecs = 2000;
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cmd = SUNXI_MMC_CMD_START |
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SUNXI_MMC_CMD_UPCLK_ONLY |
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SUNXI_MMC_CMD_WAIT_PRE_OVER;
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writel(cmd, &mmchost->reg->cmd);
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while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
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if (!timeout_msecs--)
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return -1;
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udelay(1000);
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}
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/* clock update sets various irq status bits, clear these */
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writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
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return 0;
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}
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static int mmc_config_clock(struct mmc *mmc, unsigned div)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned rval = readl(&mmchost->reg->clkcr);
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/* Disable Clock */
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rval &= ~SUNXI_MMC_CLK_ENABLE;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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/* Change Divider Factor */
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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rval |= div;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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/* Re-enable Clock */
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rval |= SUNXI_MMC_CLK_ENABLE;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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return 0;
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}
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static void mmc_set_ios(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int clkdiv = 0;
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debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
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mmc->bus_width, mmc->clock, mmchost->mod_clk);
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/* Change clock first */
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clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
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if (mmc->clock) {
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if (mmc_config_clock(mmc, clkdiv)) {
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mmchost->fatal_err = 1;
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return;
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}
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}
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/* Change bus width */
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if (mmc->bus_width == 8)
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writel(0x2, &mmchost->reg->width);
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else if (mmc->bus_width == 4)
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writel(0x1, &mmchost->reg->width);
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else
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writel(0x0, &mmchost->reg->width);
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}
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static int mmc_core_init(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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/* Reset controller */
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writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
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udelay(1000);
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return 0;
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}
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static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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const int reading = !!(data->flags & MMC_DATA_READ);
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const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
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SUNXI_MMC_STATUS_FIFO_FULL;
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unsigned i;
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unsigned byte_cnt = data->blocksize * data->blocks;
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unsigned timeout_msecs = 2000;
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unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
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/* Always read / write data through the CPU */
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setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
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for (i = 0; i < (byte_cnt >> 2); i++) {
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while (readl(&mmchost->reg->status) & status_bit) {
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if (!timeout_msecs--)
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return -1;
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udelay(1000);
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}
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if (reading)
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buff[i] = readl(mmchost->database);
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else
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writel(buff[i], mmchost->database);
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}
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return 0;
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}
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static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
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unsigned int done_bit, const char *what)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int status;
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do {
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status = readl(&mmchost->reg->rint);
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if (!timeout_msecs-- ||
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(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
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debug("%s timeout %x\n", what,
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status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
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return TIMEOUT;
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}
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udelay(1000);
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} while (!(status & done_bit));
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return 0;
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int cmdval = SUNXI_MMC_CMD_START;
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unsigned int timeout_msecs;
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int error = 0;
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unsigned int status = 0;
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unsigned int bytecnt = 0;
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if (mmchost->fatal_err)
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return -1;
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if (cmd->resp_type & MMC_RSP_BUSY)
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debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
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if (cmd->cmdidx == 12)
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return 0;
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if (!cmd->cmdidx)
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cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
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if (cmd->resp_type & MMC_RSP_PRESENT)
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cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
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if (cmd->resp_type & MMC_RSP_136)
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cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
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if (cmd->resp_type & MMC_RSP_CRC)
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cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
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if (data) {
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if ((u32) data->dest & 0x3) {
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error = -1;
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goto out;
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}
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cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
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if (data->flags & MMC_DATA_WRITE)
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cmdval |= SUNXI_MMC_CMD_WRITE;
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if (data->blocks > 1)
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cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
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writel(data->blocksize, &mmchost->reg->blksz);
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writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
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}
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debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
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cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
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writel(cmd->cmdarg, &mmchost->reg->arg);
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if (!data)
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writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
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/*
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* transfer data and check status
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* STATREG[2] : FIFO empty
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* STATREG[3] : FIFO full
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*/
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if (data) {
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int ret = 0;
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bytecnt = data->blocksize * data->blocks;
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debug("trans data %d bytes\n", bytecnt);
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writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
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ret = mmc_trans_data_by_cpu(mmc, data);
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if (ret) {
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error = readl(&mmchost->reg->rint) & \
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SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
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error = TIMEOUT;
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goto out;
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}
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}
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error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
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if (error)
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goto out;
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if (data) {
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timeout_msecs = 120;
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debug("cacl timeout %x msec\n", timeout_msecs);
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error = mmc_rint_wait(mmc, timeout_msecs,
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data->blocks > 1 ?
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SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
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SUNXI_MMC_RINT_DATA_OVER,
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"data");
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if (error)
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goto out;
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}
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if (cmd->resp_type & MMC_RSP_BUSY) {
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timeout_msecs = 2000;
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do {
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status = readl(&mmchost->reg->status);
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if (!timeout_msecs--) {
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debug("busy timeout\n");
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error = TIMEOUT;
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goto out;
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}
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udelay(1000);
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} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
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}
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = readl(&mmchost->reg->resp3);
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cmd->response[1] = readl(&mmchost->reg->resp2);
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cmd->response[2] = readl(&mmchost->reg->resp1);
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cmd->response[3] = readl(&mmchost->reg->resp0);
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debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
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cmd->response[3], cmd->response[2],
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cmd->response[1], cmd->response[0]);
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} else {
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cmd->response[0] = readl(&mmchost->reg->resp0);
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debug("mmc resp 0x%08x\n", cmd->response[0]);
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}
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out:
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if (error < 0) {
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writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
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mmc_update_clk(mmc);
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}
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writel(0xffffffff, &mmchost->reg->rint);
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writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
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&mmchost->reg->gctrl);
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return error;
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}
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static const struct mmc_ops sunxi_mmc_ops = {
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.send_cmd = mmc_send_cmd,
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.set_ios = mmc_set_ios,
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.init = mmc_core_init,
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};
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int sunxi_mmc_init(int sdc_no)
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{
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struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
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memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
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cfg->name = "SUNXI SD/MMC";
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cfg->ops = &sunxi_mmc_ops;
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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cfg->host_caps = MMC_MODE_4BIT;
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cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
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cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
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cfg->f_min = 400000;
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cfg->f_max = 52000000;
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mmc_resource_init(sdc_no);
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mmc_clk_io_on(sdc_no);
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if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
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return -1;
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return 0;
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}
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