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![Sam Shih](/assets/img/avatar_default.png)
Due to the pinctrl hardware of MT7622 is difference from others SoC which using the common part of mediatek pinctrl. So we need to modify the common part of mediatek pinctrl. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
193 lines
4.7 KiB
C
193 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#ifndef __PINCTRL_MEDIATEK_H__
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#define __PINCTRL_MEDIATEK_H__
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#define MTK_PINCTRL_V0 0x0
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#define MTK_PINCTRL_V1 0x1
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#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
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#define MTK_PIN(_number, _name, _drv_n) { \
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.number = _number, \
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.name = _name, \
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.drv_n = _drv_n, \
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}
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#define PINCTRL_PIN_GROUP(name, id) \
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{ \
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name, \
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id##_pins, \
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ARRAY_SIZE(id##_pins), \
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id##_funcs, \
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}
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#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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_x_bits, _sz_reg, _fixed) { \
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.s_pin = _s_pin, \
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.e_pin = _e_pin, \
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.s_addr = _s_addr, \
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.x_addrs = _x_addrs, \
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.s_bit = _s_bit, \
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.x_bits = _x_bits, \
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.sz_reg = _sz_reg, \
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.fixed = _fixed, \
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}
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/* List these attributes which could be modified for the pin */
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enum {
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PINCTRL_PIN_REG_MODE,
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PINCTRL_PIN_REG_DIR,
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PINCTRL_PIN_REG_DI,
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PINCTRL_PIN_REG_DO,
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PINCTRL_PIN_REG_SMT,
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PINCTRL_PIN_REG_PD,
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PINCTRL_PIN_REG_PU,
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PINCTRL_PIN_REG_E4,
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PINCTRL_PIN_REG_E8,
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PINCTRL_PIN_REG_IES,
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PINCTRL_PIN_REG_PULLEN,
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PINCTRL_PIN_REG_PULLSEL,
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PINCTRL_PIN_REG_DRV,
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PINCTRL_PIN_REG_MAX,
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};
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/* Group the pins by the driving current */
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enum {
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DRV_FIXED,
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DRV_GRP0,
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DRV_GRP1,
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DRV_GRP2,
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DRV_GRP3,
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DRV_GRP4,
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};
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/**
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* struct mtk_pin_field - the structure that holds the information of the field
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* used to describe the attribute for the pin
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* @offset: the register offset relative to the base address
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* @mask: the mask used to filter out the field from the register
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* @bitpos: the start bit relative to the register
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* @next: the indication that the field would be extended to the
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next register
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*/
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struct mtk_pin_field {
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u32 offset;
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u32 mask;
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u8 bitpos;
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u8 next;
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};
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/**
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* struct mtk_pin_field_calc - the structure that holds the range providing
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* the guide used to look up the relevant field
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* @s_pin: the start pin within the range
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* @e_pin: the end pin within the range
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* @s_addr: the start address for the range
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* @x_addrs: the address distance between two consecutive registers
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* within the range
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* @s_bit: the start bit for the first register within the range
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* @x_bits: the bit distance between two consecutive pins within
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* the range
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* @sz_reg: the size of bits in a register
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* @fixed: the consecutive pins share the same bits with the 1st
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* pin
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*/
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struct mtk_pin_field_calc {
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u16 s_pin;
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u16 e_pin;
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u32 s_addr;
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u8 x_addrs;
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u8 s_bit;
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u8 x_bits;
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u8 sz_reg;
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u8 fixed;
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};
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/**
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* struct mtk_pin_reg_calc - the structure that holds all ranges used to
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* determine which register the pin would make use of
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* for certain pin attribute.
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* @range: the start address for the range
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* @nranges: the number of items in the range
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*/
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struct mtk_pin_reg_calc {
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const struct mtk_pin_field_calc *range;
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unsigned int nranges;
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};
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/**
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* struct mtk_pin_desc - the structure that providing information
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* for each pin of chips
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* @number: unique pin number from the global pin number space
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* @name: name for this pin
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* @drv_n: the index with the driving group
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*/
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struct mtk_pin_desc {
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unsigned int number;
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const char *name;
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u8 drv_n;
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};
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/**
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* struct mtk_group_desc - generic pin group descriptor
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* @name: name of the pin group
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* @pins: array of pins that belong to the group
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* @num_pins: number of pins in the group
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* @data: pin controller driver specific data
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*/
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struct mtk_group_desc {
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const char *name;
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int *pins;
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int num_pins;
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void *data;
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};
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/**
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* struct mtk_function_desc - generic function descriptor
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* @name: name of the function
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* @group_names: array of pin group names
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* @num_group_names: number of pin group names
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*/
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struct mtk_function_desc {
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const char *name;
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const char * const *group_names;
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int num_group_names;
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};
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/* struct mtk_pin_soc - the structure that holds SoC-specific data */
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struct mtk_pinctrl_soc {
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const char *name;
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const struct mtk_pin_reg_calc *reg_cal;
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const struct mtk_pin_desc *pins;
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int npins;
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const struct mtk_group_desc *grps;
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int ngrps;
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const struct mtk_function_desc *funcs;
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int nfuncs;
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int gpio_mode;
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int rev;
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};
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/**
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* struct mtk_pinctrl_priv - private data for MTK pinctrl driver
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*
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* @base: base address of the pinctrl device
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* @soc: SoC specific data
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*/
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struct mtk_pinctrl_priv {
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void __iomem *base;
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struct mtk_pinctrl_soc *soc;
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};
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extern const struct pinctrl_ops mtk_pinctrl_ops;
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/* A common read-modify-write helper for MediaTek chips */
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void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
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int mtk_pinctrl_common_probe(struct udevice *dev,
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struct mtk_pinctrl_soc *soc);
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#endif /* __PINCTRL_MEDIATEK_H__ */
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