u-boot-brain/arch/riscv
Anup Patel d2db2a8fa4 riscv: Add kconfig option to run U-Boot in S-mode
This patch adds kconfig option RISCV_SMODE to run U-Boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.

It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.

In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-05 14:13:53 +08:00
..
cpu riscv: Add kconfig option to run U-Boot in S-mode 2018-12-05 14:13:53 +08:00
dts riscv: dts: Add ae350_32.dts for RV32I 2018-11-26 13:57:55 +08:00
include/asm riscv: Add kconfig option to run U-Boot in S-mode 2018-12-05 14:13:53 +08:00
lib riscv: Add kconfig option to run U-Boot in S-mode 2018-12-05 14:13:53 +08:00
config.mk riscv: enable -fdata-sections 2018-11-26 13:57:29 +08:00
Kconfig riscv: Add kconfig option to run U-Boot in S-mode 2018-12-05 14:13:53 +08:00
Makefile riscv: set -march and -mabi based on the Kconfig configuration 2018-11-26 13:57:29 +08:00