mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
4c42557021
Move arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sbc-regs.h>
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#include <asm/arch/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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#if !defined(CONFIG_SPL_BUILD)
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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#endif
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0);
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writel(0x0400bc01, SBBASE1);
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writel(0x0800bf01, SBBASE3);
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#if !defined(CONFIG_SPL_BUILD)
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/* enable access to sub memory when boot swap is on */
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sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
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#endif
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sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
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}
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