mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
4c42557021
Move arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* Copyright (C) 2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <../drivers/mtd/nand/denali.h>
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static void nand_denali_wp_disable(void)
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{
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#ifdef CONFIG_NAND_DENALI
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/*
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* Since the boot rom enables the write protection for NAND boot mode,
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* it must be disabled somewhere for "nand write", "nand erase", etc.
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* The workaround is here to not disturb the Denali NAND controller
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* driver just for a really SoC-specific thing.
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*/
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void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
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writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
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#endif
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}
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int board_late_init(void)
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{
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puts("MODE: ");
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC1:
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printf("eMMC Boot\n");
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setenv("bootmode", "emmcboot");
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break;
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case BOOT_DEVICE_NAND:
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printf("NAND Boot\n");
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setenv("bootmode", "nandboot");
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nand_denali_wp_disable();
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break;
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case BOOT_DEVICE_NOR:
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printf("NOR Boot\n");
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setenv("bootmode", "norboot");
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break;
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default:
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printf("Unsupported Boot Mode\n");
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return -1;
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}
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return 0;
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}
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