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![Simon Glass](/assets/img/avatar_default.png)
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
619 lines
18 KiB
C
619 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* Conversion to DM
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* (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <hang.h>
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#include <malloc.h>
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#include <command.h>
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#include <net.h>
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#include <miiphy.h>
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#include <asm/fec.h>
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#include <asm/immap.h>
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#include <linux/mii.h>
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#undef ET_DEBUG
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#undef MII_DEBUG
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MAXBLR_SIZE 1520
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#define LAST_PKTBUFSRX PKTBUFSRX - 1
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#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
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#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
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DECLARE_GLOBAL_DATA_PTR;
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static void init_eth_info(struct fec_info_s *info)
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{
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#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
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static u32 tmp;
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if (info->index == 0)
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tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
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else
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info->rxbd = (cbd_t *)DBUF_LENGTH;
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/* setup Receive and Transmit buffer descriptor */
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info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
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tmp = (u32)info->rxbd;
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info->txbd =
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(cbd_t *)((u32)info->txbd + tmp +
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(PKTBUFSRX * sizeof(cbd_t)));
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tmp = (u32)info->txbd;
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info->txbuf =
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(char *)((u32)info->txbuf + tmp +
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(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
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tmp = (u32)info->txbuf;
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#else
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info->rxbd =
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(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
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(PKTBUFSRX * sizeof(cbd_t)));
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info->txbd =
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(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
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(TX_BUF_CNT * sizeof(cbd_t)));
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info->txbuf =
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(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
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#endif
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#ifdef ET_DEBUG
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printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
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#endif
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info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
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}
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static void fec_reset(struct fec_info_s *info)
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{
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volatile fec_t *fecp = (fec_t *)(info->iobase);
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int i;
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fecp->ecr = FEC_ECR_RESET;
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for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i)
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udelay(1);
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if (i == FEC_RESET_DELAY)
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printf("FEC_RESET_DELAY timeout\n");
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}
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static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd)
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{
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bd_t *bd = gd->bd;
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if ((dup_spd >> 16) == FULL) {
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/* Set maximum frame length */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
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FEC_RCR_PROM | 0x100;
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fecp->tcr = FEC_TCR_FDEN;
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} else {
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/* Half duplex mode */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
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FEC_RCR_MII_MODE | FEC_RCR_DRT;
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fecp->tcr &= ~FEC_TCR_FDEN;
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}
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if ((dup_spd & 0xFFFF) == _100BASET) {
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#ifdef CONFIG_MCF5445x
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fecp->rcr &= ~0x200; /* disabled 10T base */
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#endif
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#ifdef MII_DEBUG
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printf("100Mbps\n");
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#endif
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bd->bi_ethspeed = 100;
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} else {
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#ifdef CONFIG_MCF5445x
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fecp->rcr |= 0x200; /* enabled 10T base */
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#endif
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#ifdef MII_DEBUG
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printf("10Mbps\n");
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#endif
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bd->bi_ethspeed = 10;
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}
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}
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#ifdef ET_DEBUG
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static void dbg_fec_regs(struct udevice *dev)
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{
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *)(info->iobase);
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printf("=====\n");
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printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
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printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
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printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
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printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
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printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
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printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
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printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
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printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
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printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
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printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
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printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
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printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
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printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
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printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
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printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
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printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
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printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
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printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
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printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
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printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
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printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
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printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
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printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
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printf("\n");
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printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
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fecp->rmon_t_drop);
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printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
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fecp->rmon_t_packets);
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printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
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fecp->rmon_t_bc_pkt);
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printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
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fecp->rmon_t_mc_pkt);
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printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
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fecp->rmon_t_crc_align);
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printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
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fecp->rmon_t_undersize);
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printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
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fecp->rmon_t_oversize);
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printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
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fecp->rmon_t_frag);
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printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
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fecp->rmon_t_jab);
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printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
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fecp->rmon_t_col);
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printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
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fecp->rmon_t_p64);
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printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
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fecp->rmon_t_p65to127);
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printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
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fecp->rmon_t_p128to255);
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printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
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fecp->rmon_t_p256to511);
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printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
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fecp->rmon_t_p512to1023);
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printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
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fecp->rmon_t_p1024to2047);
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printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
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fecp->rmon_t_p_gte2048);
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printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
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fecp->rmon_t_octets);
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printf("\n");
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printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
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fecp->ieee_t_drop);
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printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
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fecp->ieee_t_frame_ok);
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printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
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fecp->ieee_t_1col);
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printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
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fecp->ieee_t_mcol);
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printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
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fecp->ieee_t_def);
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printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
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fecp->ieee_t_lcol);
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printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
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fecp->ieee_t_excol);
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printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
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fecp->ieee_t_macerr);
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printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
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fecp->ieee_t_cserr);
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printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
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fecp->ieee_t_sqe);
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printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
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fecp->ieee_t_fdxfc);
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printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
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fecp->ieee_t_octets_ok);
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printf("\n");
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printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
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fecp->rmon_r_drop);
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printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
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fecp->rmon_r_packets);
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printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
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fecp->rmon_r_bc_pkt);
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printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
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fecp->rmon_r_mc_pkt);
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printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
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fecp->rmon_r_crc_align);
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printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
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fecp->rmon_r_undersize);
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printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
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fecp->rmon_r_oversize);
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printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
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fecp->rmon_r_frag);
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printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
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fecp->rmon_r_jab);
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printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
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fecp->rmon_r_p64);
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printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
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fecp->rmon_r_p65to127);
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printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
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fecp->rmon_r_p128to255);
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printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
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fecp->rmon_r_p256to511);
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printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
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fecp->rmon_r_p512to1023);
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printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
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fecp->rmon_r_p1024to2047);
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printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
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fecp->rmon_r_p_gte2048);
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printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
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fecp->rmon_r_octets);
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printf("\n");
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printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
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fecp->ieee_r_drop);
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printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
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fecp->ieee_r_frame_ok);
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printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
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fecp->ieee_r_crc);
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printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
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fecp->ieee_r_align);
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printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
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fecp->ieee_r_macerr);
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printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
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fecp->ieee_r_fdxfc);
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printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
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fecp->ieee_r_octets_ok);
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printf("\n\n\n");
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}
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#endif
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int mcffec_init(struct udevice *dev)
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{
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *) (info->iobase);
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int rval, i;
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uchar ea[6];
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fecpin_setclear(info, 1);
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fec_reset(info);
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#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
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defined (CONFIG_SYS_DISCOVER_PHY)
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mii_init();
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set_fec_duplex_speed(fecp, info->dup_spd);
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#else
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#ifndef CONFIG_SYS_DISCOVER_PHY
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set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
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#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
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#endif /* CONFIG_CMD_MII || CONFIG_MII */
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set station address */
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if (info->index == 0)
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rval = eth_env_get_enetaddr("ethaddr", ea);
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else
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rval = eth_env_get_enetaddr("eth1addr", ea);
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if (!rval) {
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puts("Please set a valid MAC address\n");
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return -EINVAL;
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}
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fecp->palr =
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(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
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fecp->paur = (ea[4] << 24) | (ea[5] << 16);
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/* Clear unicast address hash table */
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fecp->iaur = 0;
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fecp->ialr = 0;
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/* Clear multicast address hash table */
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fecp->gaur = 0;
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fecp->galr = 0;
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/* Set maximum receive buffer size. */
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fecp->emrbr = PKT_MAXBLR_SIZE;
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/*
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* Setup Buffers and Buffer Descriptors
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*/
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info->rx_idx = 0;
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info->tx_idx = 0;
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/*
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* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings:
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* Empty, Wrap
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*/
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for (i = 0; i < PKTBUFSRX; i++) {
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info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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info->rxbd[i].cbd_datlen = 0; /* Reset */
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info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
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}
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info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/*
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* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings:
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* Last, Tx CRC
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*/
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for (i = 0; i < TX_BUF_CNT; i++) {
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info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
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info->txbd[i].cbd_datlen = 0; /* Reset */
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info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
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}
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info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* Set receive and transmit descriptor base */
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fecp->erdsr = (unsigned int)(&info->rxbd[0]);
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fecp->etdsr = (unsigned int)(&info->txbd[0]);
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/* Now enable the transmit and receive processing */
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fecp->ecr |= FEC_ECR_ETHER_EN;
|
|
|
|
/* And last, try to fill Rx Buffer Descriptors
|
|
* Descriptor polling active
|
|
*/
|
|
fecp->rdar = 0x01000000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mcffec_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
volatile fec_t *fecp = (fec_t *)info->iobase;
|
|
int j, rc;
|
|
u16 phy_status;
|
|
|
|
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
|
|
|
|
/* section 16.9.23.3
|
|
* Wait for ready
|
|
*/
|
|
j = 0;
|
|
while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
|
|
(j < info->to_loop)) {
|
|
udelay(1);
|
|
j++;
|
|
}
|
|
if (j >= info->to_loop)
|
|
printf("TX not ready\n");
|
|
|
|
info->txbd[info->tx_idx].cbd_bufaddr = (uint)packet;
|
|
info->txbd[info->tx_idx].cbd_datlen = length;
|
|
info->txbd[info->tx_idx].cbd_sc |= BD_ENET_TX_RDY_LST;
|
|
|
|
/* Activate transmit Buffer Descriptor polling */
|
|
fecp->tdar = 0x01000000; /* Descriptor polling active */
|
|
|
|
#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
|
|
/*
|
|
* FEC unable to initial transmit data packet.
|
|
* A nop will ensure the descriptor polling active completed.
|
|
* CF Internal RAM has shorter cycle access than DRAM. If use
|
|
* DRAM as Buffer descriptor and data, a nop is a must.
|
|
* Affect only V2 and V3.
|
|
*/
|
|
__asm__ ("nop");
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_UNIFY_CACHE
|
|
icache_invalid();
|
|
#endif
|
|
|
|
j = 0;
|
|
while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
|
|
(j < info->to_loop)) {
|
|
udelay(1);
|
|
j++;
|
|
}
|
|
if (j >= info->to_loop)
|
|
printf("TX timeout\n");
|
|
|
|
#ifdef ET_DEBUG
|
|
printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
|
|
__FILE__, __LINE__, __func__, j,
|
|
info->txbd[info->tx_idx].cbd_sc,
|
|
(info->txbd[info->tx_idx].cbd_sc & 0x003C) >> 2);
|
|
#endif
|
|
|
|
/* return only status bits */
|
|
rc = (info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
|
|
info->tx_idx = (info->tx_idx + 1) % TX_BUF_CNT;
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
volatile fec_t *fecp = (fec_t *)info->iobase;
|
|
int length = -1;
|
|
|
|
for (;;) {
|
|
#ifdef CONFIG_SYS_UNIFY_CACHE
|
|
icache_invalid();
|
|
#endif
|
|
/* If nothing received - leave for() loop */
|
|
if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY)
|
|
break;
|
|
|
|
length = info->rxbd[info->rx_idx].cbd_datlen;
|
|
|
|
if (info->rxbd[info->rx_idx].cbd_sc & 0x003f) {
|
|
printf("%s[%d] err: %x\n",
|
|
__func__, __LINE__,
|
|
info->rxbd[info->rx_idx].cbd_sc);
|
|
} else {
|
|
length -= 4;
|
|
|
|
/*
|
|
* Pass the buffer ptr up to the protocol layers.
|
|
*/
|
|
*packetp = net_rx_packets[info->rx_idx];
|
|
|
|
fecp->eir |= FEC_EIR_RXF;
|
|
}
|
|
|
|
/* Give the buffer back to the FEC. */
|
|
info->rxbd[info->rx_idx].cbd_datlen = 0;
|
|
|
|
/* wrap around buffer index when necessary */
|
|
if (info->rx_idx == LAST_PKTBUFSRX) {
|
|
info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
|
|
info->rx_idx = 0;
|
|
} else {
|
|
info->rxbd[info->rx_idx].cbd_sc = BD_ENET_RX_EMPTY;
|
|
info->rx_idx++;
|
|
}
|
|
|
|
/* Try to fill Buffer Descriptors
|
|
* Descriptor polling active
|
|
*/
|
|
fecp->rdar = 0x01000000;
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
static void mcffec_halt(struct udevice *dev)
|
|
{
|
|
struct fec_info_s *info = dev->priv;
|
|
|
|
fec_reset(info);
|
|
fecpin_setclear(info, 0);
|
|
|
|
info->rx_idx = 0;
|
|
info->tx_idx = 0;
|
|
|
|
memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
|
|
memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
|
|
memset(info->txbuf, 0, DBUF_LENGTH);
|
|
}
|
|
|
|
static const struct eth_ops mcffec_ops = {
|
|
.start = mcffec_init,
|
|
.send = mcffec_send,
|
|
.recv = mcffec_recv,
|
|
.stop = mcffec_halt,
|
|
};
|
|
|
|
/*
|
|
* Boot sequence, called just after mcffec_ofdata_to_platdata,
|
|
* as DM way, it replaces old mcffec_initialize.
|
|
*/
|
|
static int mcffec_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct fec_info_s *info = dev->priv;
|
|
int node = dev_of_offset(dev);
|
|
int retval, fec_idx;
|
|
const u32 *val;
|
|
|
|
info->index = dev->seq;
|
|
info->iobase = pdata->iobase;
|
|
info->phy_addr = -1;
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "mii-base", NULL);
|
|
if (val) {
|
|
u32 fec_iobase;
|
|
|
|
fec_idx = fdt32_to_cpu(*val);
|
|
if (fec_idx == info->index) {
|
|
fec_iobase = info->iobase;
|
|
} else {
|
|
printf("mii base != base address, fec_idx %d\n",
|
|
fec_idx);
|
|
retval = fec_get_base_addr(fec_idx, &fec_iobase);
|
|
if (retval)
|
|
return retval;
|
|
}
|
|
info->miibase = fec_iobase;
|
|
}
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "phy-addr", NULL);
|
|
if (val)
|
|
info->phy_addr = fdt32_to_cpu(*val);
|
|
|
|
val = fdt_getprop(gd->fdt_blob, node, "timeout-loop", NULL);
|
|
if (val)
|
|
info->to_loop = fdt32_to_cpu(*val);
|
|
|
|
init_eth_info(info);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
info->bus = mdio_alloc();
|
|
if (!info->bus)
|
|
return -ENOMEM;
|
|
strcpy(info->bus->name, dev->name);
|
|
info->bus->read = mcffec_miiphy_read;
|
|
info->bus->write = mcffec_miiphy_write;
|
|
|
|
retval = mdio_register(info->bus);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mcffec_remove(struct udevice *dev)
|
|
{
|
|
struct fec_info_s *priv = dev_get_priv(dev);
|
|
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Boot sequence, called 1st
|
|
*/
|
|
static int mcffec_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const u32 *val;
|
|
|
|
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
|
|
/* Default to 10Mbit/s */
|
|
pdata->max_speed = 10;
|
|
|
|
val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
|
|
"max-speed", NULL);
|
|
if (val)
|
|
pdata->max_speed = fdt32_to_cpu(*val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mcffec_ids[] = {
|
|
{ .compatible = "fsl,mcf-fec" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(mcffec) = {
|
|
.name = "mcffec",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mcffec_ids,
|
|
.ofdata_to_platdata = mcffec_ofdata_to_platdata,
|
|
.probe = mcffec_probe,
|
|
.remove = mcffec_remove,
|
|
.ops = &mcffec_ops,
|
|
.priv_auto_alloc_size = sizeof(struct fec_info_s),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|