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![Simon Glass](/assets/img/avatar_default.png)
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
256 lines
5.3 KiB
C
256 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments CDCE913/925/937/949 clock synthesizer driver
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Tero Kristo <t-kristo@ti.com>
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*
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* Based on Linux kernel clk-cdce925.c.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk-uclass.h>
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#include <i2c.h>
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#include <dm/device_compat.h>
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#define MAX_NUMBER_OF_PLLS 4
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#define MAX_NUMER_OF_OUTPUTS 9
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#define CDCE9XX_REG_GLOBAL1 0x01
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#define CDCE9XX_REG_Y1SPIPDIVH 0x02
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#define CDCE9XX_REG_PDIV1L 0x03
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#define CDCE9XX_REG_XCSEL 0x05
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#define CDCE9XX_PDIV1_H_MASK 0x3
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#define CDCE9XX_REG_PDIV(clk) (0x16 + (((clk) - 1) & 1) + \
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((clk) - 1) / 2 * 0x10)
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#define CDCE9XX_PDIV_MASK 0x7f
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#define CDCE9XX_BYTE_TRANSFER BIT(7)
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struct cdce9xx_chip_info {
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int num_plls;
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int num_outputs;
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};
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struct cdce9xx_clk_data {
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struct udevice *i2c;
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struct cdce9xx_chip_info *chip;
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u32 xtal_rate;
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};
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static const struct cdce9xx_chip_info cdce913_chip_info = {
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.num_plls = 1, .num_outputs = 3,
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};
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static const struct cdce9xx_chip_info cdce925_chip_info = {
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.num_plls = 2, .num_outputs = 5,
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};
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static const struct cdce9xx_chip_info cdce937_chip_info = {
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.num_plls = 3, .num_outputs = 7,
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};
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static const struct cdce9xx_chip_info cdce949_chip_info = {
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.num_plls = 4, .num_outputs = 9,
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};
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static int cdce9xx_reg_read(struct udevice *dev, u8 addr, u8 *buf)
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{
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struct cdce9xx_clk_data *data = dev_get_priv(dev);
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int ret;
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ret = dm_i2c_read(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, buf, 1);
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if (ret)
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dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
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addr, ret);
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return ret;
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}
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static int cdce9xx_reg_write(struct udevice *dev, u8 addr, u8 val)
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{
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struct cdce9xx_clk_data *data = dev_get_priv(dev);
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int ret;
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ret = dm_i2c_write(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, &val, 1);
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if (ret)
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dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
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addr, ret);
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return ret;
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}
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static int cdce9xx_clk_of_xlate(struct clk *clk,
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struct ofnode_phandle_args *args)
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{
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struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
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if (args->args_count != 1)
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return -EINVAL;
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if (args->args[0] > data->chip->num_outputs)
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return -EINVAL;
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clk->id = args->args[0];
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return 0;
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}
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static int cdce9xx_clk_probe(struct udevice *dev)
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{
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struct cdce9xx_clk_data *data = dev_get_priv(dev);
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struct cdce9xx_chip_info *chip = (void *)dev_get_driver_data(dev);
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int ret;
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u32 val;
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struct clk clk;
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val = (u32)dev_read_addr_ptr(dev);
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ret = i2c_get_chip(dev->parent, val, 1, &data->i2c);
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if (ret) {
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dev_err(dev, "I2C probe failed.\n");
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return ret;
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}
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data->chip = chip;
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ret = clk_get_by_index(dev, 0, &clk);
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data->xtal_rate = clk_get_rate(&clk);
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val = dev_read_u32_default(dev, "xtal-load-pf", -1);
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if (val >= 0)
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cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3);
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return 0;
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}
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static u16 cdce9xx_clk_get_pdiv(struct clk *clk)
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{
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u8 val;
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u16 pdiv;
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int ret;
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if (clk->id == 0) {
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ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
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if (ret)
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return 0;
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pdiv = (val & CDCE9XX_PDIV1_H_MASK) << 8;
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ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV1L, &val);
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if (ret)
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return 0;
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pdiv |= val;
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} else {
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ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
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&val);
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if (ret)
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return 0;
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pdiv = val & CDCE9XX_PDIV_MASK;
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}
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return pdiv;
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}
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static u32 cdce9xx_clk_get_parent_rate(struct clk *clk)
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{
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struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
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return data->xtal_rate;
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}
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static ulong cdce9xx_clk_get_rate(struct clk *clk)
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{
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u32 parent_rate;
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u16 pdiv;
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parent_rate = cdce9xx_clk_get_parent_rate(clk);
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pdiv = cdce9xx_clk_get_pdiv(clk);
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return parent_rate / pdiv;
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}
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static ulong cdce9xx_clk_set_rate(struct clk *clk, ulong rate)
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{
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u32 parent_rate;
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int pdiv;
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u32 diff;
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u8 val;
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int ret;
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parent_rate = cdce9xx_clk_get_parent_rate(clk);
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pdiv = parent_rate / rate;
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diff = rate - parent_rate / pdiv;
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if (rate - parent_rate / (pdiv + 1) < diff)
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pdiv++;
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if (clk->id == 0) {
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ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
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if (ret)
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return ret;
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val &= ~CDCE9XX_PDIV1_H_MASK;
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val |= (pdiv >> 8);
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ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, val);
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if (ret)
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return ret;
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ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV1L,
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(pdiv & 0xff));
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if (ret)
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return ret;
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} else {
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ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
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&val);
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if (ret)
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return ret;
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val &= ~CDCE9XX_PDIV_MASK;
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val |= pdiv;
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ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV(clk->id),
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val);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct udevice_id cdce9xx_clk_of_match[] = {
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{ .compatible = "ti,cdce913", .data = (u32)&cdce913_chip_info },
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{ .compatible = "ti,cdce925", .data = (u32)&cdce925_chip_info },
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{ .compatible = "ti,cdce937", .data = (u32)&cdce937_chip_info },
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{ .compatible = "ti,cdce949", .data = (u32)&cdce949_chip_info },
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{ /* sentinel */ },
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};
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static const struct clk_ops cdce9xx_clk_ops = {
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.of_xlate = cdce9xx_clk_of_xlate,
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.get_rate = cdce9xx_clk_get_rate,
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.set_rate = cdce9xx_clk_set_rate,
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};
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U_BOOT_DRIVER(cdce9xx_clk) = {
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.name = "cdce9xx-clk",
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.id = UCLASS_CLK,
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.of_match = cdce9xx_clk_of_match,
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.probe = cdce9xx_clk_probe,
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.priv_auto_alloc_size = sizeof(struct cdce9xx_clk_data),
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.ops = &cdce9xx_clk_ops,
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};
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