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![Ryder Lee](/assets/img/avatar_default.png)
This adds power domain (scpsys) support for MT7623 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
407 lines
9.2 KiB
C
407 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <power-domain-uclass.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <linux/iopoll.h>
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#include <dt-bindings/power/mt7623-power.h>
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#include <dt-bindings/power/mt7629-power.h>
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#define SPM_EN (0xb16 << 16 | 0x1)
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_MFG_PWR_CON 0x0214
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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#define SPM_CONN_PWR_CON 0x0280
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#define SPM_BDP_PWR_CON 0x029c
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#define SPM_ETH_PWR_CON 0x02a0
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#define SPM_HIF_PWR_CON 0x02a4
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#define SPM_IFR_MSC_PWR_CON 0x02a8
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#define SPM_ETHSYS_PWR_CON 0x2e0
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#define SPM_HIF0_PWR_CON 0x2e4
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#define SPM_HIF1_PWR_CON 0x2e8
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#define SPM_PWR_STATUS 0x60c
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#define SPM_PWR_STATUS_2ND 0x610
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#define PWR_RST_B_BIT BIT(0)
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#define PWR_ISO_BIT BIT(1)
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#define PWR_ON_BIT BIT(2)
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#define PWR_ON_2ND_BIT BIT(3)
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#define PWR_CLK_DIS_BIT BIT(4)
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#define PWR_STATUS_CONN BIT(1)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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#define PWR_STATUS_VDEC BIT(7)
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#define PWR_STATUS_BDP BIT(14)
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#define PWR_STATUS_ETH BIT(15)
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#define PWR_STATUS_HIF BIT(16)
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#define PWR_STATUS_IFR_MSC BIT(17)
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#define PWR_STATUS_ETHSYS BIT(24)
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#define PWR_STATUS_HIF0 BIT(25)
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#define PWR_STATUS_HIF1 BIT(26)
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/* Infrasys configuration */
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#define INFRA_TOPDCM_CTRL 0x10
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#define INFRA_TOPAXI_PROT_EN 0x220
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#define INFRA_TOPAXI_PROT_STA1 0x228
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#define DCM_TOP_EN BIT(0)
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enum scp_domain_type {
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SCPSYS_MT7623,
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SCPSYS_MT7629,
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};
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struct scp_domain;
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struct scp_domain_data {
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struct scp_domain *scpd;
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u32 sta_mask;
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int ctl_offs;
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u32 sram_pdn_bits;
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u32 sram_pdn_ack_bits;
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u32 bus_prot_mask;
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};
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struct scp_domain {
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void __iomem *base;
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void __iomem *infracfg;
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enum scp_domain_type type;
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struct scp_domain_data *data;
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};
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static struct scp_domain_data scp_domain_mt7623[] = {
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[MT7623_POWER_DOMAIN_CONN] = {
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = SPM_CONN_PWR_CON,
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.bus_prot_mask = BIT(8) | BIT(2),
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},
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[MT7623_POWER_DOMAIN_DISP] = {
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.bus_prot_mask = BIT(2),
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},
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[MT7623_POWER_DOMAIN_MFG] = {
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT7623_POWER_DOMAIN_VDEC] = {
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT7623_POWER_DOMAIN_ISP] = {
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT7623_POWER_DOMAIN_BDP] = {
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.sta_mask = PWR_STATUS_BDP,
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.ctl_offs = SPM_BDP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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},
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[MT7623_POWER_DOMAIN_ETH] = {
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.sta_mask = PWR_STATUS_ETH,
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.ctl_offs = SPM_ETH_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT7623_POWER_DOMAIN_HIF] = {
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.sta_mask = PWR_STATUS_HIF,
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.ctl_offs = SPM_HIF_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT7623_POWER_DOMAIN_IFR_MSC] = {
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.sta_mask = PWR_STATUS_IFR_MSC,
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.ctl_offs = SPM_IFR_MSC_PWR_CON,
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},
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};
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static struct scp_domain_data scp_domain_mt7629[] = {
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[MT7629_POWER_DOMAIN_ETHSYS] = {
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.sta_mask = PWR_STATUS_ETHSYS,
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.ctl_offs = SPM_ETHSYS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bus_prot_mask = (BIT(3) | BIT(17)),
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},
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[MT7629_POWER_DOMAIN_HIF0] = {
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.sta_mask = PWR_STATUS_HIF0,
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.ctl_offs = SPM_HIF0_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bus_prot_mask = GENMASK(25, 24),
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},
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[MT7629_POWER_DOMAIN_HIF1] = {
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.sta_mask = PWR_STATUS_HIF1,
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.ctl_offs = SPM_HIF1_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bus_prot_mask = GENMASK(28, 26),
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},
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};
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/**
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* This function enables the bus protection bits for disabled power
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* domains so that the system does not hang when some unit accesses the
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* bus while in power down.
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*/
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static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
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u32 mask)
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{
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u32 val;
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clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);
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return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
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(val & mask) == mask, 100);
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}
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static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg,
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u32 mask)
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{
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u32 val;
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clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask);
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return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
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!(val & mask), 100);
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}
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static int scpsys_domain_is_on(struct scp_domain_data *data)
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{
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struct scp_domain *scpd = data->scpd;
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u32 sta = readl(scpd->base + SPM_PWR_STATUS) &
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data->sta_mask;
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u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) &
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data->sta_mask;
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/*
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* A domain is on when both status bits are set. If only one is set
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* return an error. This happens while powering up a domain
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*/
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if (sta && sta2)
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return true;
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if (!sta && !sta2)
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return false;
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return -EINVAL;
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}
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static int scpsys_power_on(struct power_domain *power_domain)
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{
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struct scp_domain *scpd = dev_get_priv(power_domain->dev);
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struct scp_domain_data *data = &scpd->data[power_domain->id];
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void __iomem *ctl_addr = scpd->base + data->ctl_offs;
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u32 pdn_ack = data->sram_pdn_ack_bits;
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u32 val;
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int ret, tmp;
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writel(SPM_EN, scpd->base);
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val = readl(ctl_addr);
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val |= PWR_ON_BIT;
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writel(val, ctl_addr);
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val |= PWR_ON_2ND_BIT;
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writel(val, ctl_addr);
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ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0,
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100);
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if (ret < 0)
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return ret;
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val &= ~PWR_CLK_DIS_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ISO_BIT;
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writel(val, ctl_addr);
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val |= PWR_RST_B_BIT;
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writel(val, ctl_addr);
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val &= ~data->sram_pdn_bits;
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writel(val, ctl_addr);
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ret = readl_poll_timeout(ctl_addr, tmp, !(tmp & pdn_ack), 100);
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if (ret < 0)
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return ret;
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if (data->bus_prot_mask) {
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ret = mtk_infracfg_clear_bus_protection(scpd->infracfg,
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data->bus_prot_mask);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int scpsys_power_off(struct power_domain *power_domain)
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{
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struct scp_domain *scpd = dev_get_priv(power_domain->dev);
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struct scp_domain_data *data = &scpd->data[power_domain->id];
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void __iomem *ctl_addr = scpd->base + data->ctl_offs;
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u32 pdn_ack = data->sram_pdn_ack_bits;
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u32 val;
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int ret, tmp;
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if (data->bus_prot_mask) {
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ret = mtk_infracfg_set_bus_protection(scpd->infracfg,
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data->bus_prot_mask);
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if (ret)
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return ret;
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}
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val = readl(ctl_addr);
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val |= data->sram_pdn_bits;
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writel(val, ctl_addr);
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ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
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100);
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if (ret < 0)
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return ret;
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val |= PWR_ISO_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_RST_B_BIT;
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writel(val, ctl_addr);
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val |= PWR_CLK_DIS_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ON_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ON_2ND_BIT;
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writel(val, ctl_addr);
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ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int scpsys_power_request(struct power_domain *power_domain)
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{
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struct scp_domain *scpd = dev_get_priv(power_domain->dev);
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struct scp_domain_data *data;
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data = &scpd->data[power_domain->id];
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data->scpd = scpd;
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return 0;
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}
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static int scpsys_power_free(struct power_domain *power_domain)
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{
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return 0;
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}
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static int mtk_power_domain_hook(struct udevice *dev)
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{
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struct scp_domain *scpd = dev_get_priv(dev);
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scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
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switch (scpd->type) {
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case SCPSYS_MT7623:
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scpd->data = scp_domain_mt7623;
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break;
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case SCPSYS_MT7629:
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scpd->data = scp_domain_mt7629;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mtk_power_domain_probe(struct udevice *dev)
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{
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struct ofnode_phandle_args args;
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struct scp_domain *scpd = dev_get_priv(dev);
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struct regmap *regmap;
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struct clk_bulk bulk;
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int err;
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scpd->base = dev_read_addr_ptr(dev);
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if (!scpd->base)
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return -ENOENT;
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err = mtk_power_domain_hook(dev);
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if (err)
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return err;
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/* get corresponding syscon phandle */
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err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args);
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if (err)
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return err;
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regmap = syscon_node_to_regmap(args.node);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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scpd->infracfg = regmap_get_range(regmap, 0);
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if (!scpd->infracfg)
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return -ENOENT;
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/* enable Infra DCM */
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setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);
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err = clk_get_bulk(dev, &bulk);
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if (err)
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return err;
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return clk_enable_bulk(&bulk);
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}
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static const struct udevice_id mtk_power_domain_ids[] = {
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{
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.compatible = "mediatek,mt7623-scpsys",
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.data = SCPSYS_MT7623,
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},
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{
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.compatible = "mediatek,mt7629-scpsys",
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.data = SCPSYS_MT7629,
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},
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{ /* sentinel */ }
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};
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struct power_domain_ops mtk_power_domain_ops = {
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.free = scpsys_power_free,
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.off = scpsys_power_off,
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.on = scpsys_power_on,
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.request = scpsys_power_request,
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};
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U_BOOT_DRIVER(mtk_power_domain) = {
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.name = "mtk_power_domain",
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.id = UCLASS_POWER_DOMAIN,
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.ops = &mtk_power_domain_ops,
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.probe = mtk_power_domain_probe,
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.of_match = mtk_power_domain_ids,
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.priv_auto_alloc_size = sizeof(struct scp_domain),
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};
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