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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
585 lines
17 KiB
C
585 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008-2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP Semiconductor
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr.h>
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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static unsigned int
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compute_cas_latency(const unsigned int ctrl_num,
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const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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unsigned int i;
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unsigned int common_caslat;
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unsigned int caslat_actual;
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unsigned int retry = 16;
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unsigned int tmp = ~0;
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const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
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#ifdef CONFIG_SYS_FSL_DDR3
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const unsigned int taamax = 20000;
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#else
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const unsigned int taamax = 18000;
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#endif
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/* compute the common CAS latency supported between slots */
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks)
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tmp &= dimm_params[i].caslat_x;
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}
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common_caslat = tmp;
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/* validate if the memory clk is in the range of dimms */
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if (mclk_ps < outpdimm->tckmin_x_ps) {
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printf("DDR clock (MCLK cycle %u ps) is faster than "
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"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
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mclk_ps, outpdimm->tckmin_x_ps);
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}
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#ifdef CONFIG_SYS_FSL_DDR4
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if (mclk_ps > outpdimm->tckmax_ps) {
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printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
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mclk_ps, outpdimm->tckmax_ps);
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}
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#endif
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/* determine the acutal cas latency */
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caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
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/* check if the dimms support the CAS latency */
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while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
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caslat_actual++;
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retry--;
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}
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/* once the caculation of caslat_actual is completed
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* we must verify that this CAS latency value does not
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* exceed tAAmax, which is 20 ns for all DDR3 speed grades,
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* 18ns for all DDR4 speed grades.
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*/
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if (caslat_actual * mclk_ps > taamax) {
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printf("The chosen cas latency %d is too large\n",
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caslat_actual);
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}
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outpdimm->lowest_common_spd_caslat = caslat_actual;
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debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
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return 0;
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}
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#else /* for DDR1 and DDR2 */
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static unsigned int
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compute_cas_latency(const unsigned int ctrl_num,
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const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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int i;
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const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
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unsigned int lowest_good_caslat;
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unsigned int not_ok;
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unsigned int temp1, temp2;
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debug("using mclk_ps = %u\n", mclk_ps);
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if (mclk_ps > outpdimm->tckmax_ps) {
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printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
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mclk_ps, outpdimm->tckmax_ps);
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}
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/*
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* Compute a CAS latency suitable for all DIMMs
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*
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* Strategy for SPD-defined latencies: compute only
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* CAS latency defined by all DIMMs.
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*/
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
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* operation.
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*/
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temp1 = 0xFF;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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temp2 = 0;
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temp2 |= 1 << dimm_params[i].caslat_x;
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temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
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temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
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/*
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* If there was no entry for X-2 (X-1) in
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* the SPD, then caslat_x_minus_2
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* (caslat_x_minus_1) contains either 255 or
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* 0xFFFFFFFF because that's what the glorious
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* __ilog2 function returns for an input of 0.
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* On 32-bit PowerPC, left shift counts with bit
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* 26 set (that the value of 255 or 0xFFFFFFFF
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* will have), cause the destination register to
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* be 0. That is why this works.
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*/
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temp1 &= temp2;
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}
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}
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/*
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* Step 2: check each common CAS latency against tCK of each
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* DIMM's SPD.
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*/
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lowest_good_caslat = 0;
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temp2 = 0;
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while (temp1) {
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not_ok = 0;
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temp2 = __ilog2(temp1);
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debug("checking common caslat = %u\n", temp2);
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/* Check if this CAS latency will work on all DIMMs at tCK. */
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for (i = 0; i < number_of_dimms; i++) {
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if (!dimm_params[i].n_ranks)
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continue;
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if (dimm_params[i].caslat_x == temp2) {
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if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
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temp2, i, mclk_ps,
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dimm_params[i].tckmin_x_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_x_minus_1 == temp2) {
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unsigned int tckmin_x_minus_1_ps
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= dimm_params[i].tckmin_x_minus_1_ps;
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if (mclk_ps >= tckmin_x_minus_1_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
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temp2, i, mclk_ps,
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tckmin_x_minus_1_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_x_minus_2 == temp2) {
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unsigned int tckmin_x_minus_2_ps
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= dimm_params[i].tckmin_x_minus_2_ps;
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if (mclk_ps >= tckmin_x_minus_2_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
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temp2, i, mclk_ps,
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tckmin_x_minus_2_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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}
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if (!not_ok)
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lowest_good_caslat = temp2;
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temp1 &= ~(1 << temp2);
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}
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debug("lowest common SPD-defined CAS latency = %u\n",
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lowest_good_caslat);
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outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
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/*
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* Compute a common 'de-rated' CAS latency.
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*
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* The strategy here is to find the *highest* dereated cas latency
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* with the assumption that all of the DIMMs will support a dereated
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* CAS latency higher than or equal to their lowest dereated value.
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*/
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++)
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temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
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outpdimm->highest_common_derated_caslat = temp1;
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debug("highest common dereated CAS latency = %u\n", temp1);
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return 0;
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}
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#endif
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/*
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* compute_lowest_common_dimm_parameters()
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*
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* Determine the worst-case DIMM timing parameters from the set of DIMMs
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* whose parameters have been computed into the array pointed to
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* by dimm_params.
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*/
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unsigned int
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compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
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const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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const unsigned int number_of_dimms)
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{
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unsigned int i, j;
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unsigned int tckmin_x_ps = 0;
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unsigned int tckmax_ps = 0xFFFFFFFF;
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unsigned int trcd_ps = 0;
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unsigned int trp_ps = 0;
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unsigned int tras_ps = 0;
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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unsigned int taamin_ps = 0;
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#endif
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#ifdef CONFIG_SYS_FSL_DDR4
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unsigned int twr_ps = 15000;
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unsigned int trfc1_ps = 0;
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unsigned int trfc2_ps = 0;
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unsigned int trfc4_ps = 0;
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unsigned int trrds_ps = 0;
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unsigned int trrdl_ps = 0;
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unsigned int tccdl_ps = 0;
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unsigned int trfc_slr_ps = 0;
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#else
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unsigned int twr_ps = 0;
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unsigned int twtr_ps = 0;
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unsigned int trfc_ps = 0;
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unsigned int trrd_ps = 0;
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unsigned int trtp_ps = 0;
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#endif
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unsigned int trc_ps = 0;
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unsigned int refresh_rate_ps = 0;
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unsigned int extended_op_srt = 1;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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unsigned int tis_ps = 0;
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unsigned int tih_ps = 0;
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unsigned int tds_ps = 0;
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unsigned int tdh_ps = 0;
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unsigned int tdqsq_max_ps = 0;
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unsigned int tqhs_ps = 0;
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#endif
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unsigned int temp1, temp2;
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unsigned int additive_latency = 0;
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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/*
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* If there are no ranks on this DIMM,
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* it probably doesn't exist, so skip it.
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*/
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if (dimm_params[i].n_ranks == 0) {
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temp1++;
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continue;
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}
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if (dimm_params[i].n_ranks == 4 && i != 0) {
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printf("Found Quad-rank DIMM in wrong bank, ignored."
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" Software may not run as expected.\n");
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temp1++;
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continue;
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}
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/*
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* check if quad-rank DIMM is plugged if
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* CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
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* Only the board with proper design is capable
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*/
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#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
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if (dimm_params[i].n_ranks == 4 && \
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CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
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printf("Found Quad-rank DIMM, not able to support.");
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temp1++;
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continue;
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}
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#endif
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/*
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* Find minimum tckmax_ps to find fastest slow speed,
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* i.e., this is the slowest the whole system can go.
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*/
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tckmax_ps = min(tckmax_ps,
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(unsigned int)dimm_params[i].tckmax_ps);
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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taamin_ps = max(taamin_ps,
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(unsigned int)dimm_params[i].taa_ps);
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#endif
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tckmin_x_ps = max(tckmin_x_ps,
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(unsigned int)dimm_params[i].tckmin_x_ps);
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trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
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trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
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tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
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#ifdef CONFIG_SYS_FSL_DDR4
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trfc1_ps = max(trfc1_ps,
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(unsigned int)dimm_params[i].trfc1_ps);
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trfc2_ps = max(trfc2_ps,
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(unsigned int)dimm_params[i].trfc2_ps);
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trfc4_ps = max(trfc4_ps,
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(unsigned int)dimm_params[i].trfc4_ps);
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trrds_ps = max(trrds_ps,
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(unsigned int)dimm_params[i].trrds_ps);
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trrdl_ps = max(trrdl_ps,
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(unsigned int)dimm_params[i].trrdl_ps);
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tccdl_ps = max(tccdl_ps,
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(unsigned int)dimm_params[i].tccdl_ps);
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trfc_slr_ps = max(trfc_slr_ps,
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(unsigned int)dimm_params[i].trfc_slr_ps);
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#else
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twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
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twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
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trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
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trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
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trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
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#endif
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trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
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tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
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tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
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tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
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tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
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/*
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* Find maximum tdqsq_max_ps to find slowest.
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*
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* FIXME: is finding the slowest value the correct
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* strategy for this parameter?
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*/
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tdqsq_max_ps = max(tdqsq_max_ps,
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(unsigned int)dimm_params[i].tdqsq_max_ps);
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#endif
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refresh_rate_ps = max(refresh_rate_ps,
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(unsigned int)dimm_params[i].refresh_rate_ps);
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/* extended_op_srt is either 0 or 1, 0 having priority */
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extended_op_srt = min(extended_op_srt,
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(unsigned int)dimm_params[i].extended_op_srt);
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}
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outpdimm->ndimms_present = number_of_dimms - temp1;
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if (temp1 == number_of_dimms) {
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debug("no dimms this memory controller\n");
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return 0;
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}
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outpdimm->tckmin_x_ps = tckmin_x_ps;
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outpdimm->tckmax_ps = tckmax_ps;
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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outpdimm->taamin_ps = taamin_ps;
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#endif
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outpdimm->trcd_ps = trcd_ps;
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outpdimm->trp_ps = trp_ps;
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outpdimm->tras_ps = tras_ps;
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#ifdef CONFIG_SYS_FSL_DDR4
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outpdimm->trfc1_ps = trfc1_ps;
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outpdimm->trfc2_ps = trfc2_ps;
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outpdimm->trfc4_ps = trfc4_ps;
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outpdimm->trrds_ps = trrds_ps;
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outpdimm->trrdl_ps = trrdl_ps;
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outpdimm->tccdl_ps = tccdl_ps;
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outpdimm->trfc_slr_ps = trfc_slr_ps;
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#else
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outpdimm->twtr_ps = twtr_ps;
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outpdimm->trfc_ps = trfc_ps;
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outpdimm->trrd_ps = trrd_ps;
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outpdimm->trtp_ps = trtp_ps;
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#endif
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outpdimm->twr_ps = twr_ps;
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outpdimm->trc_ps = trc_ps;
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outpdimm->refresh_rate_ps = refresh_rate_ps;
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outpdimm->extended_op_srt = extended_op_srt;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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outpdimm->tis_ps = tis_ps;
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outpdimm->tih_ps = tih_ps;
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outpdimm->tds_ps = tds_ps;
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outpdimm->tdh_ps = tdh_ps;
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outpdimm->tdqsq_max_ps = tdqsq_max_ps;
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outpdimm->tqhs_ps = tqhs_ps;
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#endif
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/* Determine common burst length for all DIMMs. */
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temp1 = 0xff;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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temp1 &= dimm_params[i].burst_lengths_bitmask;
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}
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}
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outpdimm->all_dimms_burst_lengths_bitmask = temp1;
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/* Determine if all DIMMs registered buffered. */
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temp1 = temp2 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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if (dimm_params[i].registered_dimm) {
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temp1 = 1;
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#ifndef CONFIG_SPL_BUILD
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printf("Detected RDIMM %s\n",
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dimm_params[i].mpart);
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#endif
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} else {
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temp2 = 1;
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#ifndef CONFIG_SPL_BUILD
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printf("Detected UDIMM %s\n",
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dimm_params[i].mpart);
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#endif
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}
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}
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}
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outpdimm->all_dimms_registered = 0;
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outpdimm->all_dimms_unbuffered = 0;
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if (temp1 && !temp2) {
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outpdimm->all_dimms_registered = 1;
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} else if (!temp1 && temp2) {
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outpdimm->all_dimms_unbuffered = 1;
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} else {
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printf("ERROR: Mix of registered buffered and unbuffered "
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|
"DIMMs detected!\n");
|
|
}
|
|
|
|
temp1 = 0;
|
|
if (outpdimm->all_dimms_registered)
|
|
for (j = 0; j < 16; j++) {
|
|
outpdimm->rcw[j] = dimm_params[0].rcw[j];
|
|
for (i = 1; i < number_of_dimms; i++) {
|
|
if (!dimm_params[i].n_ranks)
|
|
continue;
|
|
if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
|
|
temp1 = 1;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (temp1 != 0)
|
|
printf("ERROR: Mix different RDIMM detected!\n");
|
|
|
|
/* calculate cas latency for all DDR types */
|
|
if (compute_cas_latency(ctrl_num, dimm_params,
|
|
outpdimm, number_of_dimms))
|
|
return 1;
|
|
|
|
/* Determine if all DIMMs ECC capable. */
|
|
temp1 = 1;
|
|
for (i = 0; i < number_of_dimms; i++) {
|
|
if (dimm_params[i].n_ranks &&
|
|
!(dimm_params[i].edc_config & EDC_ECC)) {
|
|
temp1 = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (temp1) {
|
|
debug("all DIMMs ECC capable\n");
|
|
} else {
|
|
debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
|
|
}
|
|
outpdimm->all_dimms_ecc_capable = temp1;
|
|
|
|
/*
|
|
* Compute additive latency.
|
|
*
|
|
* For DDR1, additive latency should be 0.
|
|
*
|
|
* For DDR2, with ODT enabled, use "a value" less than ACTTORW,
|
|
* which comes from Trcd, and also note that:
|
|
* add_lat + caslat must be >= 4
|
|
*
|
|
* For DDR3, we use the AL=0
|
|
*
|
|
* When to use additive latency for DDR2:
|
|
*
|
|
* I. Because you are using CL=3 and need to do ODT on writes and
|
|
* want functionality.
|
|
* 1. Are you going to use ODT? (Does your board not have
|
|
* additional termination circuitry for DQ, DQS, DQS_,
|
|
* DM, RDQS, RDQS_ for x4/x8 configs?)
|
|
* 2. If so, is your lowest supported CL going to be 3?
|
|
* 3. If so, then you must set AL=1 because
|
|
*
|
|
* WL >= 3 for ODT on writes
|
|
* RL = AL + CL
|
|
* WL = RL - 1
|
|
* ->
|
|
* WL = AL + CL - 1
|
|
* AL + CL - 1 >= 3
|
|
* AL + CL >= 4
|
|
* QED
|
|
*
|
|
* RL >= 3 for ODT on reads
|
|
* RL = AL + CL
|
|
*
|
|
* Since CL aren't usually less than 2, AL=0 is a minimum,
|
|
* so the WL-derived AL should be the -- FIXME?
|
|
*
|
|
* II. Because you are using auto-precharge globally and want to
|
|
* use additive latency (posted CAS) to get more bandwidth.
|
|
* 1. Are you going to use auto-precharge mode globally?
|
|
*
|
|
* Use addtivie latency and compute AL to be 1 cycle less than
|
|
* tRCD, i.e. the READ or WRITE command is in the cycle
|
|
* immediately following the ACTIVATE command..
|
|
*
|
|
* III. Because you feel like it or want to do some sort of
|
|
* degraded-performance experiment.
|
|
* 1. Do you just want to use additive latency because you feel
|
|
* like it?
|
|
*
|
|
* Validation: AL is less than tRCD, and within the other
|
|
* read-to-precharge constraints.
|
|
*/
|
|
|
|
additive_latency = 0;
|
|
|
|
#if defined(CONFIG_SYS_FSL_DDR2)
|
|
if ((outpdimm->lowest_common_spd_caslat < 4) &&
|
|
(picos_to_mclk(ctrl_num, trcd_ps) >
|
|
outpdimm->lowest_common_spd_caslat)) {
|
|
additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
|
|
outpdimm->lowest_common_spd_caslat;
|
|
if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
|
|
additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
|
|
debug("setting additive_latency to %u because it was "
|
|
" greater than tRCD_ps\n", additive_latency);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Validate additive latency
|
|
*
|
|
* AL <= tRCD(min)
|
|
*/
|
|
if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
|
|
printf("Error: invalid additive latency exceeds tRCD(min).\n");
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
|
|
* WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
|
|
* ADD_LAT (the register) must be set to a value less
|
|
* than ACTTORW if WL = 1, then AL must be set to 1
|
|
* RD_TO_PRE (the register) must be set to a minimum
|
|
* tRTP + AL if AL is nonzero
|
|
*/
|
|
|
|
/*
|
|
* Additive latency will be applied only if the memctl option to
|
|
* use it.
|
|
*/
|
|
outpdimm->additive_latency = additive_latency;
|
|
|
|
debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
|
|
debug("trcd_ps = %u\n", outpdimm->trcd_ps);
|
|
debug("trp_ps = %u\n", outpdimm->trp_ps);
|
|
debug("tras_ps = %u\n", outpdimm->tras_ps);
|
|
#ifdef CONFIG_SYS_FSL_DDR4
|
|
debug("trfc1_ps = %u\n", trfc1_ps);
|
|
debug("trfc2_ps = %u\n", trfc2_ps);
|
|
debug("trfc4_ps = %u\n", trfc4_ps);
|
|
debug("trrds_ps = %u\n", trrds_ps);
|
|
debug("trrdl_ps = %u\n", trrdl_ps);
|
|
debug("tccdl_ps = %u\n", tccdl_ps);
|
|
debug("trfc_slr_ps = %u\n", trfc_slr_ps);
|
|
#else
|
|
debug("twtr_ps = %u\n", outpdimm->twtr_ps);
|
|
debug("trfc_ps = %u\n", outpdimm->trfc_ps);
|
|
debug("trrd_ps = %u\n", outpdimm->trrd_ps);
|
|
#endif
|
|
debug("twr_ps = %u\n", outpdimm->twr_ps);
|
|
debug("trc_ps = %u\n", outpdimm->trc_ps);
|
|
|
|
return 0;
|
|
}
|