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![Marek Behún](/assets/img/avatar_default.png)
Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
155 lines
3.2 KiB
C
155 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell Armada 37xx SoC Time Base Generator clocks
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*
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* Marek Behun <marek.behun@nic.cz>
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*
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* Based on Linux driver by:
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#define NUM_TBG 4
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#define TBG_CTRL0 0x4
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#define TBG_CTRL1 0x8
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#define TBG_CTRL7 0x20
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#define TBG_CTRL8 0x30
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#define TBG_DIV_MASK 0x1FF
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#define TBG_A_REFDIV 0
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#define TBG_B_REFDIV 16
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#define TBG_A_FBDIV 2
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#define TBG_B_FBDIV 18
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#define TBG_A_VCODIV_SE 0
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#define TBG_B_VCODIV_SE 16
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#define TBG_A_VCODIV_DIFF 1
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#define TBG_B_VCODIV_DIFF 17
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struct tbg_def {
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const char *name;
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u32 refdiv_offset;
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u32 fbdiv_offset;
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u32 vcodiv_reg;
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u32 vcodiv_offset;
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};
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static const struct tbg_def tbg[NUM_TBG] = {
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{"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
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{"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
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{"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
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{"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
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};
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struct a37xx_tbgclk {
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ulong rates[NUM_TBG];
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unsigned int mult[NUM_TBG];
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unsigned int div[NUM_TBG];
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};
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static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg)
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{
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u32 val;
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val = readl(reg + TBG_CTRL0);
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return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2;
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}
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static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg)
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{
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u32 val;
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unsigned int div;
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val = readl(reg + TBG_CTRL7);
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div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK;
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if (div == 0)
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div = 1;
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val = readl(reg + ptbg->vcodiv_reg);
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div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK);
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return div;
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}
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static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
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{
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struct a37xx_tbgclk *priv = dev_get_priv(clk->dev);
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if (clk->id >= NUM_TBG)
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return -ENODEV;
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return priv->rates[clk->id];
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}
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#if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
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int armada_37xx_tbg_clk_dump(struct udevice *dev)
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{
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struct a37xx_tbgclk *priv = dev_get_priv(dev);
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int i;
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for (i = 0; i < NUM_TBG; ++i)
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printf(" %s at %lu Hz\n", tbg[i].name,
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priv->rates[i]);
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printf("\n");
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return 0;
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}
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#endif
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static int armada_37xx_tbg_clk_probe(struct udevice *dev)
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{
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struct a37xx_tbgclk *priv = dev_get_priv(dev);
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void __iomem *reg;
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ulong xtal;
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int i;
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reg = dev_read_addr_ptr(dev);
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if (!reg) {
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dev_err(dev, "no io address\n");
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return -ENODEV;
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}
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xtal = (ulong)get_ref_clk() * 1000000;
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for (i = 0; i < NUM_TBG; ++i) {
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unsigned int mult, div;
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mult = tbg_get_mult(reg, &tbg[i]);
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div = tbg_get_div(reg, &tbg[i]);
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priv->rates[i] = (xtal * mult) / div;
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}
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return 0;
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}
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static const struct clk_ops armada_37xx_tbg_clk_ops = {
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.get_rate = armada_37xx_tbg_clk_get_rate,
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};
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static const struct udevice_id armada_37xx_tbg_clk_ids[] = {
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{ .compatible = "marvell,armada-3700-tbg-clock" },
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{}
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};
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U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
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.name = "armada_37xx_tbg_clk",
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.id = UCLASS_CLK,
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.of_match = armada_37xx_tbg_clk_ids,
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.ops = &armada_37xx_tbg_clk_ops,
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.priv_auto_alloc_size = sizeof(struct a37xx_tbgclk),
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.probe = armada_37xx_tbg_clk_probe,
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};
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