mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
/*
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* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* Rockchip SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <sdhci.h>
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#include <clk.h>
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/* 400KHz is max freq for card ID etc. Use that as min */
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#define EMMC_MIN_FREQ 400000
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struct rockchip_sdhc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_sdhc {
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struct sdhci_host host;
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void *base;
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};
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static int arasan_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
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struct rockchip_sdhc *prv = dev_get_priv(dev);
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struct sdhci_host *host = &prv->host;
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int max_frequency, ret;
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struct clk clk;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
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host->name = dev->name;
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host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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max_frequency = dtplat->max_frequency;
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
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#else
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max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
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ret = clk_get_by_index(dev, 0, &clk);
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#endif
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if (!ret) {
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ret = clk_set_rate(&clk, max_frequency);
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if (IS_ERR_VALUE(ret))
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printf("%s clk set rate fail!\n", __func__);
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} else {
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printf("%s fail to get clk\n", __func__);
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}
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
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host->max_clk = max_frequency;
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/*
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* The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
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* doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
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* check for other bus-width values.
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*/
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if (host->bus_width == 8)
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host->host_caps |= MMC_MODE_8BIT;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
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host->mmc = &plat->mmc;
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if (ret)
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return ret;
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host->mmc->priv = &prv->host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return sdhci_probe(dev);
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}
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static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct sdhci_host *host = dev_get_priv(dev);
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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#endif
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return 0;
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}
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static int rockchip_sdhci_bind(struct udevice *dev)
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{
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struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-5.1" },
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{ }
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};
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U_BOOT_DRIVER(arasan_sdhci_drv) = {
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.name = "rockchip_rk3399_sdhci_5_1",
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.id = UCLASS_MMC,
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.of_match = arasan_sdhci_ids,
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.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
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.ops = &sdhci_ops,
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.bind = rockchip_sdhci_bind,
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.probe = arasan_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
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.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
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};
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