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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
335 lines
7.7 KiB
C
335 lines
7.7 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* (C) Copyright 2003 (440GX port)
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#if (UIC_MAX > 3)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
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UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
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#elif (UIC_MAX > 2)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
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#elif (UIC_MAX > 1)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
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#else
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#define UICB0_ALL 0
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* CPM interrupt vector functions.
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*/
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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int count;
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};
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static struct irq_action irq_vecs[UIC_MAX * 32];
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u32 get_dcr(u16);
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void set_dcr(u16, u32);
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#if defined(CONFIG_440)
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/* SPRN changed in 440 */
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtspr 0x03f,%0" : : "r" (val));
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}
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#else /* !defined(CONFIG_440) */
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static __inline__ void set_pit(unsigned long val)
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{
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asm volatile("mtpit %0" : : "r" (val));
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}
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static __inline__ void set_tcr(unsigned long val)
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{
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asm volatile("mttcr %0" : : "r" (val));
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}
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtevpr %0" : : "r" (val));
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}
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#endif /* defined(CONFIG_440 */
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int interrupt_init_cpu (unsigned *decrementer_count)
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{
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int vec;
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unsigned long val;
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/* decrementer is automatically reloaded */
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*decrementer_count = 0;
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/*
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* Mark all irqs as free
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*/
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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irq_vecs[vec].count = 0;
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}
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#ifdef CONFIG_4xx
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/*
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* Init PIT
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*/
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#if defined(CONFIG_440)
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val = mfspr( tcr );
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val &= (~0x04400000); /* clear DIS & ARE */
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mtspr( tcr, val );
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mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
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mtspr( decar, 0 ); /* clear reload */
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mtspr( tsr, 0x08000000 ); /* clear DEC status */
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val = gd->bd->bi_intfreq/1000; /* 1 msec */
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mtspr( decar, val ); /* Set auto-reload value */
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mtspr( dec, val ); /* Set inital val */
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#else
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set_pit(gd->bd->bi_intfreq / 1000);
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#endif
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#endif /* CONFIG_4xx */
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#ifdef CONFIG_ADCIOP
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/*
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* Init PIT
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*/
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set_pit(66000);
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#endif
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/*
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* Enable PIT
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*/
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val = mfspr(tcr);
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val |= 0x04400000;
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mtspr(tcr, val);
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/*
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* Set EVPR to 0
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*/
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set_evpr(0x00000000);
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
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#endif
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return (0);
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}
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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{
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u32 uic_msr;
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u32 msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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set_dcr(uic_base + UIC_ER,
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get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec));
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printf("Masking bogus interrupt vector %d"
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" (UIC_BASE=0x%x)\n", vec, uic_base);
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}
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/*
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* After servicing the interrupt, we have to remove the
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* status indicator
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*/
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set_dcr(uic_base + UIC_SR, UIC_MASK(vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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u32 uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uic0msr);
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#if (UIC_MAX > 1)
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if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
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uic_interrupt(UIC1_DCR_BASE, 32);
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#endif
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#if (UIC_MAX > 2)
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if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
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uic_interrupt(UIC2_DCR_BASE, 64);
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#endif
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#if (UIC_MAX > 3)
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if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
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uic_interrupt(UIC3_DCR_BASE, 96);
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#endif
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if (uic_msr & ~(UICB0_ALL))
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uic_interrupt(UIC0_DCR_BASE, 0);
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mtdcr(uic0sr, uic_msr);
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return;
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}
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/*
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* Install and free a interrupt handler.
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*/
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void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
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{
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/*
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* Print warning when replacing with a different irq vector
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*/
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if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
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printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
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vec, (uint) handler, (uint) irq_vecs[vec].handler);
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}
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irq_vecs[vec].handler = handler;
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irq_vecs[vec].arg = arg;
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
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#endif
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debug("Install interrupt for vector %d ==> %p\n", vec, handler);
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}
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void irq_free_handler (int vec)
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{
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debug("Free interrupt for vector %d ==> %p\n",
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vec, irq_vecs[vec].handler);
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
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#endif
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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}
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void timer_interrupt_cpu (struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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}
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#if defined(CONFIG_CMD_IRQ)
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int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int vec;
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printf ("Interrupt-Information:\n");
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printf ("Nr Routine Arg Count\n");
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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if (irq_vecs[vec].handler != NULL) {
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printf ("%02d %08lx %08lx %d\n",
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vec,
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(ulong)irq_vecs[vec].handler,
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(ulong)irq_vecs[vec].arg,
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irq_vecs[vec].count);
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}
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}
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return 0;
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}
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#endif
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