mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
5ccd29c367
This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
|
|
* Copyright 2009 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*
|
|
*/
|
|
|
|
#ifndef _ASM_CONFIG_H_
|
|
#define _ASM_CONFIG_H_
|
|
|
|
#ifndef CONFIG_MAX_MEM_MAPPED
|
|
#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
|
|
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
|
|
#else
|
|
#define CONFIG_MAX_MEM_MAPPED (256 << 20)
|
|
#endif
|
|
#endif
|
|
|
|
/* Check if boards need to enable FSL DMA engine for SDRAM init */
|
|
#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
|
|
#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
|
|
((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
|
|
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
|
|
#define CONFIG_FSL_DMA
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
|
|
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
|
|
#define CONFIG_MAX_CPUS 2
|
|
#elif defined(CONFIG_PPC_P4080)
|
|
#define CONFIG_MAX_CPUS 8
|
|
#else
|
|
#define CONFIG_MAX_CPUS 1
|
|
#endif
|
|
|
|
/*
|
|
* Provide a default boot page translation virtual address that lines up with
|
|
* Freescale's default e500 reset page.
|
|
*/
|
|
#if (defined(CONFIG_E500) && defined(CONFIG_MP))
|
|
#ifndef CONFIG_BPTR_VIRT_ADDR
|
|
#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
|
|
#endif
|
|
#endif
|
|
|
|
/* Relocation to SDRAM works on all PPC boards */
|
|
#define CONFIG_RELOC_FIXUP_WORKS
|
|
|
|
#endif /* _ASM_CONFIG_H_ */
|