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https://github.com/brain-hackers/u-boot-brain
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77b351cd0f
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EMIF_DEFS_H_
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#define _EMIF_DEFS_H_
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#include <asm/arch/hardware.h>
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typedef struct {
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dv_reg ERCSR;
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dv_reg AWCCR;
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dv_reg SDBCR;
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dv_reg SDRCR;
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dv_reg AB1CR;
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dv_reg AB2CR;
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dv_reg AB3CR;
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dv_reg AB4CR;
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dv_reg SDTIMR;
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dv_reg DDRSR;
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dv_reg DDRPHYCR;
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dv_reg DDRPHYSR;
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dv_reg TOTAR;
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dv_reg TOTACTR;
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dv_reg DDRPHYID_REV;
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dv_reg SDSRETR;
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dv_reg EIRR;
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dv_reg EIMR;
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dv_reg EIMSR;
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dv_reg EIMCR;
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dv_reg IOCTRLR;
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dv_reg IOSTATR;
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u_int8_t RSVD0[8];
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dv_reg NANDFCR;
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dv_reg NANDFSR;
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u_int8_t RSVD1[8];
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dv_reg NANDF1ECC;
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dv_reg NANDF2ECC;
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dv_reg NANDF3ECC;
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dv_reg NANDF4ECC;
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u_int8_t RSVD2[60];
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dv_reg NAND4BITECCLOAD;
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dv_reg NAND4BITECC1;
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dv_reg NAND4BITECC2;
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dv_reg NAND4BITECC3;
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dv_reg NAND4BITECC4;
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dv_reg NANDERRADD1;
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dv_reg NANDERRADD2;
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dv_reg NANDERRVAL1;
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dv_reg NANDERRVAL2;
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} emif_registers;
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typedef emif_registers *emifregs;
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#endif
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