mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
8974ff1a60
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need around 18ms, common code only delay 10ms, so need to delay extra 8ms. Otherwise voltage switch will timeout when wait for data0 line. This IO voltage switch time depends on board design, depend on the PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF capacitance. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
254 lines
3.3 KiB
Plaintext
254 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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/ {
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binman: binman {
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multiple-images;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0} {
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u-boot,dm-pre-reloc;
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u-boot,dm-spl;
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};
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&clk {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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&osc_24m {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&aips1 {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&aips2 {
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u-boot,dm-spl;
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};
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&aips3 {
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u-boot,dm-spl;
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};
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&iomuxc {
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u-boot,dm-spl;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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&pinctrl_reg_usdhc2_vmmc {
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2_gpio {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc3 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart2 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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fsl,signal-voltage-switch-extra-delay-ms = <8>;
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};
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&usdhc3 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
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u-boot,dm-spl;
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};
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&pinctrl_i2c1 {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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&fec1 {
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phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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&binman {
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u-boot-spl-ddr {
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filename = "u-boot-spl-ddr.bin";
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pad-byte = <0xff>;
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align-size = <4>;
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align = <4>;
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u-boot-spl {
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align-end = <4>;
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};
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blob_1: blob-ext@1 {
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filename = "lpddr4_pmu_train_1d_imem.bin";
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size = <0x8000>;
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};
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blob_2: blob-ext@2 {
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filename = "lpddr4_pmu_train_1d_dmem.bin";
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size = <0x4000>;
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};
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blob_3: blob-ext@3 {
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filename = "lpddr4_pmu_train_2d_imem.bin";
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size = <0x8000>;
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};
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blob_4: blob-ext@4 {
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filename = "lpddr4_pmu_train_2d_dmem.bin";
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size = <0x4000>;
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};
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};
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flash {
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mkimage {
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args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
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blob {
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filename = "u-boot-spl-ddr.bin";
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};
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};
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};
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itb {
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filename = "u-boot.itb";
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fit {
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description = "Configuration to load ATF before U-Boot";
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#address-cells = <1>;
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fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
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images {
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uboot {
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description = "U-Boot (64-bit)";
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type = "standalone";
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arch = "arm64";
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compression = "none";
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load = <CONFIG_SYS_TEXT_BASE>;
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uboot_blob: blob-ext {
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filename = "u-boot-nodtb.bin";
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};
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};
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atf {
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description = "ARM Trusted Firmware";
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type = "firmware";
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arch = "arm64";
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compression = "none";
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load = <0x920000>;
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entry = <0x920000>;
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atf_blob: blob-ext {
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filename = "bl31.bin";
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};
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};
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fdt {
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description = "NAME";
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type = "flat_dt";
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compression = "none";
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uboot_fdt_blob: blob-ext {
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filename = "u-boot.dtb";
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};
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};
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};
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configurations {
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default = "conf";
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conf {
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description = "NAME";
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firmware = "uboot";
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loadables = "atf";
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fdt = "fdt";
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};
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};
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};
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};
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};
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