mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
4a5a7fcac2
It was observed that when booting Linux kernel on Intel Cherry Hill board, unexpected crash happens quite randomly. Sometimes kernel just oops, while sometimes kernel throws MCE errors and hangs: mce: [Hardware Error]: Machine check events logged mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151 mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0 mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363 This looks like a hardware error per mcelog. After debugging, it seems turning off turbo mode on the processor does not expose this behavior, although U-Boot runs OK with turbo mode on. Suspect it is related to an errata of Braswell processor. To fix this, remove the Braswell cpu driver which does the turbo mode configuration, and switch to use the generic cpu-x86 driver. Also there is a configuration option in the FSP that turns on the turbo mode and that has been turned off too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
215 lines
4.8 KiB
Plaintext
215 lines
4.8 KiB
Plaintext
/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <asm/arch-braswell/fsp/fsp_configs.h>
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Intel Cherry Hill";
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compatible = "intel,cherryhill", "intel,braswell";
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aliases {
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serial0 = &serial;
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spi0 = &spi;
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};
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = "/serial";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <1>;
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intel,apic-id = <2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <2>;
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intel,apic-id = <4>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <3>;
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intel,apic-id = <6>;
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};
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};
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pci {
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compatible = "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,pch9";
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#address-cells = <1>;
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#size-cells = <1>;
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irq-router {
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compatible = "intel,irq-router";
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intel,pirq-config = "ibase";
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intel,ibase-offset = <0x50>;
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intel,pirq-link = <8 8>;
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intel,pirq-mask = <0xdee0>;
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intel,pirq-routing = <
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/* Braswell PCI devices */
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PCI_BDF(0, 2, 0) INTA PIRQA
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PCI_BDF(0, 3, 0) INTA PIRQA
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PCI_BDF(0, 11, 0) INTA PIRQA
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PCI_BDF(0, 16, 0) INTA PIRQA
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PCI_BDF(0, 17, 0) INTA PIRQA
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PCI_BDF(0, 18, 0) INTA PIRQA
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PCI_BDF(0, 19, 0) INTA PIRQA
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PCI_BDF(0, 20, 0) INTA PIRQA
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PCI_BDF(0, 21, 0) INTA PIRQA
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PCI_BDF(0, 24, 0) INTA PIRQA
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PCI_BDF(0, 24, 1) INTC PIRQC
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PCI_BDF(0, 24, 2) INTD PIRQD
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PCI_BDF(0, 24, 3) INTB PIRQB
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PCI_BDF(0, 24, 4) INTA PIRQA
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PCI_BDF(0, 24, 5) INTC PIRQC
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PCI_BDF(0, 24, 6) INTD PIRQD
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PCI_BDF(0, 24, 7) INTB PIRQB
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PCI_BDF(0, 26, 0) INTA PIRQA
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PCI_BDF(0, 27, 0) INTA PIRQA
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PCI_BDF(0, 28, 0) INTA PIRQA
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PCI_BDF(0, 28, 1) INTB PIRQB
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PCI_BDF(0, 28, 2) INTC PIRQC
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PCI_BDF(0, 28, 3) INTD PIRQD
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PCI_BDF(0, 30, 0) INTA PIRQA
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PCI_BDF(0, 30, 3) INTA PIRQA
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PCI_BDF(0, 30, 4) INTA PIRQA
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PCI_BDF(0, 31, 0) INTB PIRQB
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PCI_BDF(0, 31, 3) INTB PIRQB
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/*
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* PCIe root ports downstream
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* interrupts
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*/
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(1, 0, 0) INTB PIRQB
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PCI_BDF(1, 0, 0) INTC PIRQC
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PCI_BDF(1, 0, 0) INTD PIRQD
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PCI_BDF(2, 0, 0) INTA PIRQB
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PCI_BDF(2, 0, 0) INTB PIRQC
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PCI_BDF(2, 0, 0) INTC PIRQD
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PCI_BDF(2, 0, 0) INTD PIRQA
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PCI_BDF(3, 0, 0) INTA PIRQC
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PCI_BDF(3, 0, 0) INTB PIRQD
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PCI_BDF(3, 0, 0) INTC PIRQA
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PCI_BDF(3, 0, 0) INTD PIRQB
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PCI_BDF(4, 0, 0) INTA PIRQD
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PCI_BDF(4, 0, 0) INTB PIRQA
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PCI_BDF(4, 0, 0) INTC PIRQB
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PCI_BDF(4, 0, 0) INTD PIRQC
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>;
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};
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spi: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9-spi";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "macronix,mx25u6435f", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x005e0000 0x00010000>;
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};
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};
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};
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};
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};
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fsp {
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compatible = "intel,braswell-fsp";
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fsp,memory-upd {
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compatible = "intel,braswell-fsp-memory";
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fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
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fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
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fsp,aperture-size = <APERTURE_SIZE_256MB>;
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fsp,gtt-size = <GTT_SIZE_1MB>;
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fsp,enable-dvfs;
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fsp,memory-type = <DRAM_TYPE_DDR3>;
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};
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fsp,silicon-upd {
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compatible = "intel,braswell-fsp-silicon";
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fsp,sdcard-mode = <SDCARD_MODE_PCI>;
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fsp,enable-hsuart1;
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fsp,enable-sata;
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fsp,enable-xhci;
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fsp,lpe-mode = <LPE_MODE_PCI>;
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fsp,enable-dma0;
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fsp,enable-dma1;
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fsp,enable-i2c0;
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fsp,enable-i2c1;
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fsp,enable-i2c2;
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fsp,enable-i2c3;
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fsp,enable-i2c4;
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fsp,enable-i2c5;
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fsp,enable-i2c6;
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fsp,emmc-mode = <EMMC_MODE_PCI>;
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fsp,sata-speed = <SATA_SPEED_GEN3>;
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fsp,pmic-i2c-bus = <0>;
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fsp,enable-isp;
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fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
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fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
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fsp,sd-detect-chk;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m01406c2220.dtsi"
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};
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update@1 {
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#include "microcode/m01406c3363.dtsi"
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};
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update@2 {
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#include "microcode/m01406c440a.dtsi"
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};
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};
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};
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