mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
596 lines
15 KiB
C
596 lines
15 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Adapted from FADS and other board config files to GTH by thomas@corelatus.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <watchdog.h>
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#include <mpc8xx.h>
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#include "ee_access.h"
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#include "ee_dev.h"
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#ifdef CONFIG_BDM
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#undef printf
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#define printf(a,...) /* nothing */
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#endif
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int checkboard (void)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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int Id = 0;
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int Rev = 0;
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u32 Pbdat;
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puts ("Board: ");
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/* Turn on leds and setup for reading rev and id */
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#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
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#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
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immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS);
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immap->im_cpm.cp_pbdir &= ~PB_INS;
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immap->im_cpm.cp_pbdir |= PB_OUTS;
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immap->im_cpm.cp_pbodr |= PB_OUTS;
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immap->im_cpm.cp_pbdat &= ~PB_OUTS;
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/* Hold 100 Mbit in reset until fpga is loaded */
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immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET;
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immap->im_ioport.iop_pcdir |= PC_ENET100_RESET;
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immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET;
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immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET;
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/* Turn on front led to show that we are alive */
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immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
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immap->im_ioport.iop_padir |= PA_FRONT_LED;
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immap->im_ioport.iop_paodr |= PA_FRONT_LED;
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immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
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Pbdat = immap->im_cpm.cp_pbdat;
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if (!(Pbdat & PB_ID_0))
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Id += 1;
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if (!(Pbdat & PB_ID_1))
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Id += 2;
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if (!(Pbdat & PB_ID_2))
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Id += 4;
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if (!(Pbdat & PB_ID_3))
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Id += 8;
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if (Pbdat & PB_REV_0)
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Rev += 1;
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if (Pbdat & PB_REV_1)
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Rev += 2;
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/* Turn ID off since we dont need it anymore */
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immap->im_cpm.cp_pbdat |= PB_ID_GND;
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printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id);
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return 0;
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}
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#define _NOT_USED_ 0xffffffff
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const uint sdram_table[] = {
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/* Single read, offset 0 */
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0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
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0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Burst read, Offset 0x8, 4 reads */
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0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
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0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Not used part of burst read is used for MRS, Offset 0x14 */
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0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
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/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
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/* Single write, Offset 0x18 */
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0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Burst write, Offset 0x20. 4 writes */
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0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
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0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Not used part of burst write is used for precharge, Offset 0x2C */
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0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
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/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
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/* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */
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0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Exception, Offset 0x3C */
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0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
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};
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const uint fpga_table[] = {
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/* Single read, offset 0 */
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0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
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0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
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/* Burst read, Offset 0x8 */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Single write, Offset 0x18 */
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0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
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0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
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/* Burst write, Offset 0x20. */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Period timer service. Offset 0x30. */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* Exception, Offset 0x3C */
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0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
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};
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int _initsdram (uint base, uint * noMbytes)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *mc = &immap->im_memctl;
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volatile u32 *memptr;
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mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */
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/* SDRAM in UPMA
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GPL_0 is connected instead of A19 to SDRAM.
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According to table 16-17, AMx should be 001, i.e. type 1
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and GPL_0 should hold address A10 when multiplexing */
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mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/* Perform init of sdram ( Datasheet Page 9 )
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Precharge */
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mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */
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/* Run 2 refresh cycles */
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mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
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mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
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/* Set Mode register */
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mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */
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/* Lower 2 bits are not connected to chip */
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mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */
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/* CS1, base 0x0000000 - 64 Mbyte, use UPM A */
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mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM;
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mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */
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/* Test if we really have 64 MB SDRAM */
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memptr = (u32 *) 0;
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*memptr = 0;
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memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */
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*memptr = 0x12345678;
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memptr = (u32 *) 0;
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if (*memptr == 0x12345678) {
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/* Wrapped, only have 32 MB */
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mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM;
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*noMbytes = 32;
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} else {
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/* 64 MB */
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*noMbytes = 64;
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}
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/* Setup FPGA in UPMB */
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upmconfig (UPMB, (uint *) fpga_table,
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sizeof (fpga_table) / sizeof (uint));
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/* Enable UPWAITB */
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mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */
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/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
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mc->memc_or2 = 0xffc00000 | OR_BI;
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mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V;
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/* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */
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mc->memc_or3 = 0xffc00000 | OR_BI;
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mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16;
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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void _sdramdisable (void)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_br1 = 0x00000000;
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/* maybe we should turn off upmb here or something */
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}
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/* ------------------------------------------------------------------------- */
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int initsdram (uint base, uint * noMbytes)
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{
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*noMbytes = 32;
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#ifdef CONFIG_START_IN_RAM
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/* SDRAM is already setup. Dont touch it */
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return 0;
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#else
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if (!_initsdram (base, noMbytes)) {
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return 0;
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} else {
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_sdramdisable ();
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return -1;
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}
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#endif
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}
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long int initdram (int board_type)
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{
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u32 *i;
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u32 j;
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u32 k;
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/* GTH only have SDRAM */
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uint sdramsz;
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if (!initsdram (0x00000000, &sdramsz)) {
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printf ("(%u MB SDRAM) ", sdramsz);
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} else {
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/********************************
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*SDRAM ERROR, HALT PROCESSOR
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*********************************/
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printf ("SDRAM ERROR\n");
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while (1);
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}
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#ifndef CONFIG_START_IN_RAM
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#define U32_S ((sdramsz<<18)-1)
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#if 1
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/* Do a simple memory test */
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for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
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*i = j + (j << 17);
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*(i + 1) = ~(j + (j << 18));
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}
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WATCHDOG_RESET ();
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printf (".");
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for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
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k = *i;
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if (k != (j + (j << 17))) {
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printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k);
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while (1);
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}
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k = *(i + 1);
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if (k != ~(j + (j << 18))) {
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printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x",
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(u32) i + 1, j, k);
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while (1);
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}
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}
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#endif
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WATCHDOG_RESET ();
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/* Clear memory */
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for (i = (u32 *) 0; (u32) i < U32_S; i++) {
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*i = 0;
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}
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#endif /* !start in ram */
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WATCHDOG_RESET ();
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return (sdramsz << 20);
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}
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#define POWER_OFFSET 0xF0000
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#define SW_WATCHDOG_REASON 13
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#define BOOTDATA_OFFSET 0xF8000
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#define MAX_ATTEMPTS 5
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#define FAILSAFE_BOOT 1
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#define SYSTEM_BOOT 2
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#define WRITE_FLASH16(a, d) \
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do \
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{ \
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*((volatile u16 *) (a)) = (d);\
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} while(0)
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static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
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{
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u16 data;
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volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
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if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) {
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printf ("Invalid system data %u, setting failsafe\n", System);
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System = FAILSAFE_BOOT;
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}
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if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
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printf ("Invalid boot count %u, setting 1\n", Count);
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Count = 1;
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}
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if (System == FAILSAFE_BOOT) {
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printf ("Setting failsafe boot in flash\n");
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} else {
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printf ("Setting system boot in flash\n");
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}
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printf ("Boot attempt %d\n", Count);
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data = (System << 8) | Count;
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/* AMD 16 bit */
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WRITE_FLASH16 (&flash[0x555], 0xAAAA);
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WRITE_FLASH16 (&flash[0x2AA], 0x5555);
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WRITE_FLASH16 (&flash[0x555], 0xA0A0);
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WRITE_FLASH16 (addr, data);
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}
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static void maybe_update_restart_reason (volatile u32 * addr32)
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{
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/* Update addr if sw wd restart */
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volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
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volatile u16 *addr_16 = (u16 *) addr32;
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u32 rsr;
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/* Dont reset register now */
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rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr;
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rsr >>= 24;
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if (rsr & 0x10) {
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/* Was really a sw wd restart, update reason */
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printf ("Last restart by software watchdog\n");
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/* AMD 16 bit */
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WRITE_FLASH16 (&flash[0x555], 0xAAAA);
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WRITE_FLASH16 (&flash[0x2AA], 0x5555);
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WRITE_FLASH16 (&flash[0x555], 0xA0A0);
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WRITE_FLASH16 (addr_16, 0);
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udelay (1000);
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WATCHDOG_RESET ();
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/* AMD 16 bit */
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WRITE_FLASH16 (&flash[0x555], 0xAAAA);
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WRITE_FLASH16 (&flash[0x2AA], 0x5555);
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WRITE_FLASH16 (&flash[0x555], 0xA0A0);
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WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON);
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}
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}
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static void check_restart_reason (void)
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{
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/* Update restart reason if sw watchdog was
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triggered */
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int i;
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volatile u32 *raddr;
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raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET);
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if (*raddr == 0xFFFFFFFF) {
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/* Nothing written */
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maybe_update_restart_reason (raddr);
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} else {
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/* Search for latest written reason */
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i = 0;
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while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) {
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raddr += 2;
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i++;
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}
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if (i >= 2000) {
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/* Whoa, dont write any more */
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printf ("*** No free restart reason found ***\n");
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} else {
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/* Check if written */
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if (*raddr == 0) {
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/* Erased by kernel, no new reason written */
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maybe_update_restart_reason (raddr + 2);
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}
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}
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}
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}
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static void check_boot_tries (void)
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{
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/* Count the number of boot attemps
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switch system if too many */
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int i;
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volatile u16 *addr;
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volatile u16 data;
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int failsafe = 1;
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u8 system;
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u8 count;
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addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
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if (*addr == 0xFFFF) {
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printf ("*** No bootdata exists. ***\n");
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write_bootdata (addr, FAILSAFE_BOOT, 1);
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} else {
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/* Search for latest written bootdata */
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i = 0;
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while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
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addr++;
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i++;
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}
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if (i >= 8000) {
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/* Whoa, dont write any more */
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printf ("*** No bootdata found. Not updating flash***\n");
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} else {
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/* See how many times we have tried to boot real system */
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data = *addr;
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system = data >> 8;
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count = data & 0xFF;
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if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) {
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printf ("*** Wrong system %d\n", system);
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system = FAILSAFE_BOOT;
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count = 1;
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} else {
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switch (count) {
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case 0:
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case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
/* Try same system again if needed */
|
|
count++;
|
|
break;
|
|
|
|
case 5:
|
|
/* Switch system and reset tries */
|
|
count = 1;
|
|
system = 3 - system;
|
|
printf ("***Too many boot attempts, switching system***\n");
|
|
break;
|
|
default:
|
|
/* Switch system, start over and hope it works */
|
|
printf ("***Unexpected data on addr 0x%x, %u***\n",
|
|
(u32) addr, data);
|
|
count = 1;
|
|
system = 3 - system;
|
|
}
|
|
}
|
|
write_bootdata (addr + 1, system, count);
|
|
if (system == SYSTEM_BOOT) {
|
|
failsafe = 0;
|
|
}
|
|
}
|
|
}
|
|
if (failsafe) {
|
|
printf ("Booting failsafe system\n");
|
|
setenv ("bootargs", "panic=1 root=/dev/hda7");
|
|
setenv ("bootcmd", "disk 100000 0:5;bootm 100000");
|
|
} else {
|
|
printf ("Using normal system\n");
|
|
setenv ("bootargs", "panic=1 root=/dev/hda4");
|
|
setenv ("bootcmd", "disk 100000 0:2;bootm 100000");
|
|
}
|
|
}
|
|
|
|
int misc_init_r (void)
|
|
{
|
|
u8 Rx[80];
|
|
u8 Tx[5];
|
|
int page;
|
|
int read = 0;
|
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
|
|
|
/* Kill fpga */
|
|
immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE);
|
|
immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE);
|
|
immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE);
|
|
|
|
/* Enable fpga, active low */
|
|
immap->im_ioport.iop_padat &= ~PA_FL_CE;
|
|
|
|
/* Start configuration */
|
|
immap->im_ioport.iop_padat &= ~PA_FL_CONFIG;
|
|
udelay (2);
|
|
|
|
immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE);
|
|
|
|
/* Check if we need to boot failsafe system */
|
|
check_boot_tries ();
|
|
|
|
/* Check if we need to update restart reason */
|
|
check_restart_reason ();
|
|
|
|
if (ee_init_data ()) {
|
|
printf ("EEPROM init failed\n");
|
|
return (0);
|
|
}
|
|
|
|
/* Read the pages where ethernet address is stored */
|
|
|
|
for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
|
|
/* Copy from nvram to scratchpad */
|
|
Tx[0] = RECALL_MEMORY;
|
|
Tx[1] = page;
|
|
if (ee_do_command (Tx, 2, NULL, 0, TRUE)) {
|
|
printf ("EE user page %d recall failed\n", page);
|
|
return (0);
|
|
}
|
|
|
|
Tx[0] = READ_SCRATCHPAD;
|
|
if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) {
|
|
printf ("EE user page %d read failed\n", page);
|
|
return (0);
|
|
}
|
|
/* Crc in 9:th byte */
|
|
if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
|
|
printf ("EE read failed, page %d. CRC error\n", page);
|
|
return (0);
|
|
}
|
|
read += 8;
|
|
}
|
|
|
|
/* Add eos after eth addr */
|
|
Rx[17] = 0;
|
|
|
|
printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
|
|
|
|
if ((Rx[2] != ':') |
|
|
(Rx[5] != ':') |
|
|
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
|
|
printf ("*** ethernet addr invalid, using default ***\n");
|
|
} else {
|
|
setenv ("ethaddr", (char *)Rx);
|
|
}
|
|
return (0);
|
|
}
|