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https://github.com/brain-hackers/u-boot-brain
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12d152620d
The previous version of the get_rate helper does not work if the mux clock parent is changed after the probe. This error has not been detected because this condition has not been tested. The error occurs because the set_parent helper does not change the parent of the clock device but only the clock selection register. Since changing the parent of a probed device can be tricky, the new version of the get_rate helper provides the rate of the selected clock and not that of the parent. Signed-off-by: Dario Binacchi <dariobin@libero.it>
139 lines
3.3 KiB
C
139 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/clk.h>
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#include <dm/test.h>
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#include <dm/uclass.h>
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#include <linux/err.h>
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#include <test/test.h>
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#include <test/ut.h>
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#include <sandbox-clk.h>
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/* Tests for Common Clock Framework driver */
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static int dm_test_clk_ccf(struct unit_test_state *uts)
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{
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struct clk *clk, *pclk;
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struct udevice *dev;
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long long rate;
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int ret;
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/* Get the device using the clk device */
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ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
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/* Test for clk_get_by_id() */
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ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
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ut_assertok(ret);
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ut_asserteq_str("ecspi_root", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
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/* Test for clk_get_parent_rate() */
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ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
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ut_assertok(ret);
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ut_asserteq_str("ecspi1", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
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rate = clk_get_parent_rate(clk);
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ut_asserteq(rate, 20000000);
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/* test the gate of CCF */
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ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
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ut_assertok(ret);
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ut_asserteq_str("ecspi0", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
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rate = clk_get_parent_rate(clk);
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ut_asserteq(rate, 20000000);
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/* Test the mux of CCF */
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ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
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ut_assertok(ret);
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ut_asserteq_str("usdhc1_sel", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
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rate = clk_get_parent_rate(clk);
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ut_asserteq(rate, 60000000);
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rate = clk_get_rate(clk);
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ut_asserteq(rate, 60000000);
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ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
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ut_assertok(ret);
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ret = clk_set_parent(clk, pclk);
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ut_assertok(ret);
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rate = clk_get_rate(clk);
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ut_asserteq(rate, 80000000);
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ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
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ut_assertok(ret);
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ut_asserteq_str("usdhc2_sel", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
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rate = clk_get_parent_rate(clk);
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ut_asserteq(rate, 80000000);
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pclk = clk_get_parent(clk);
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ut_asserteq_str("pll3_80m", pclk->dev->name);
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ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
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rate = clk_get_rate(clk);
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ut_asserteq(rate, 80000000);
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ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
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ut_assertok(ret);
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ret = clk_set_parent(clk, pclk);
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ut_assertok(ret);
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rate = clk_get_rate(clk);
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ut_asserteq(rate, 60000000);
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/* Test the composite of CCF */
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ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
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ut_assertok(ret);
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ut_asserteq_str("i2c", clk->dev->name);
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ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
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rate = clk_get_rate(clk);
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ut_asserteq(rate, 60000000);
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#if CONFIG_IS_ENABLED(CLK_CCF)
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/* Test clk tree enable/disable */
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ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
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ut_assertok(ret);
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ut_asserteq_str("i2c_root", clk->dev->name);
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ret = clk_enable(clk);
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ut_assertok(ret);
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ret = sandbox_clk_enable_count(clk);
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ut_asserteq(ret, 1);
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ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
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ut_assertok(ret);
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ret = sandbox_clk_enable_count(pclk);
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ut_asserteq(ret, 1);
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ret = clk_disable(clk);
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ut_assertok(ret);
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ret = sandbox_clk_enable_count(clk);
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ut_asserteq(ret, 0);
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ret = sandbox_clk_enable_count(pclk);
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ut_asserteq(ret, 0);
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#endif
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return 1;
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}
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DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);
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