mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
e04f9d0c2f
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
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{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
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{2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
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{}
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};
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/* DP-DDR DIMM */
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static const struct board_specific_parameters udimm2[] = {
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/*
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* memory controller 2
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
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{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
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{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
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{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
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{}
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
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{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
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{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
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{}
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};
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/* DP-DDR DIMM */
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static const struct board_specific_parameters rdimm2[] = {
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/*
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* memory controller 2
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
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{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
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{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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udimm0,
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udimm2,
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};
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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rdimm0,
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rdimm2,
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};
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#endif
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