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![Elaine Zhang](/assets/img/avatar_default.png)
Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
267 lines
6.2 KiB
C
267 lines
6.2 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rv1108.h>
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#include <asm/arch/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use integer mode */
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static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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{
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int id = 0;
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switch (clk_id) {
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case CLK_ARM:
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case CLK_DDR:
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id = clk_id - 1;
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break;
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case CLK_GENERAL:
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id = 2;
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break;
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default:
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printf("invalid pll id:%d\n", clk_id);
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id = -1;
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break;
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}
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return id;
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}
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static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con0, con1, con3;
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int pll_id = rv1108_pll_id(clk_id);
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struct rv1108_pll *pll = &cru->pll[pll_id];
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uint32_t freq;
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con3 = readl(&pll->con3);
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if (con3 & WORK_MODE_MASK) {
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con0 = readl(&pll->con0);
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con1 = readl(&pll->con1);
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fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
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postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
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postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
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refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
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freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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} else {
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freq = OSC_HZ;
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}
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return freq;
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}
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static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
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{
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uint32_t con = readl(&cru->clksel_con[24]);
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ulong pll_rate;
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uint8_t div;
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if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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else
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pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
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/*default set 50MHZ for gmac*/
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if (!rate)
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rate = 50000000;
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div = DIV_ROUND_UP(pll_rate, rate) - 1;
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if (div <= 0x1f)
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rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
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div << MAC_CLK_DIV_SHIFT);
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else
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debug("Unsupported div for gmac:%d\n", div);
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return DIV_TO_RATE(pll_rate, div);
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}
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static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
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{
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u32 con = readl(&cru->clksel_con[27]);
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u32 pll_rate;
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u32 div;
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if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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else
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pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
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div = DIV_ROUND_UP(pll_rate, rate) - 1;
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if (div <= 0x3f)
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rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
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div << SFC_CLK_DIV_SHIFT);
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else
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debug("Unsupported sfc clk rate:%d\n", rate);
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return DIV_TO_RATE(pll_rate, div);
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}
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static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[22]);
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div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
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CLK_SARADC_DIV_CON_WIDTH);
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return DIV_TO_RATE(OSC_HZ, div);
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}
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static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
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assert(src_clk_div < 128);
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rk_clrsetreg(&cru->clksel_con[22],
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CLK_SARADC_DIV_CON_MASK,
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src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
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return rv1108_saradc_get_clk(cru);
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}
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static ulong rv1108_clk_get_rate(struct clk *clk)
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{
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struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0 ... 63:
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return rkclk_pll_get_rate(priv->cru, clk->id);
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case SCLK_SARADC:
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return rv1108_saradc_get_clk(priv->cru);
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default:
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return -ENOENT;
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}
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}
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static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
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ulong new_rate;
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switch (clk->id) {
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case SCLK_MAC:
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new_rate = rv1108_mac_set_clk(priv->cru, rate);
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break;
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case SCLK_SFC:
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new_rate = rv1108_sfc_set_clk(priv->cru, rate);
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break;
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case SCLK_SARADC:
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new_rate = rv1108_saradc_set_clk(priv->cru, rate);
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break;
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default:
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return -ENOENT;
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}
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return new_rate;
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}
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static const struct clk_ops rv1108_clk_ops = {
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.get_rate = rv1108_clk_get_rate,
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.set_rate = rv1108_clk_set_rate,
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};
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static void rkclk_init(struct rv1108_cru *cru)
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{
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unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
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unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
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unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
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rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
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0 << MAC_CLK_DIV_SHIFT);
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printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
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}
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static int rv1108_clk_probe(struct udevice *dev)
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{
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struct rv1108_clk_priv *priv = dev_get_priv(dev);
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priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
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rkclk_init(priv->cru);
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return 0;
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}
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static int rv1108_clk_bind(struct udevice *dev)
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{
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int ret;
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struct udevice *sys_child;
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struct sysreset_reg *priv;
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/* The reset driver does not have a device node, so bind it here */
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ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
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&sys_child);
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if (ret) {
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debug("Warning: No sysreset driver: ret=%d\n", ret);
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} else {
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priv = malloc(sizeof(struct sysreset_reg));
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priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
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glb_srst_fst_val);
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priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
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glb_srst_snd_val);
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sys_child->priv = priv;
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}
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#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
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ret = offsetof(struct rk3368_cru, softrst_con[0]);
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ret = rockchip_reset_bind(dev, ret, 13);
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if (ret)
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debug("Warning: software reset driver bind faile\n");
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#endif
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return 0;
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}
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static const struct udevice_id rv1108_clk_ids[] = {
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{ .compatible = "rockchip,rv1108-cru" },
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{ }
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};
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U_BOOT_DRIVER(clk_rv1108) = {
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.name = "clk_rv1108",
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.id = UCLASS_CLK,
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.of_match = rv1108_clk_ids,
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.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
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.ops = &rv1108_clk_ops,
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.bind = rv1108_clk_bind,
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.probe = rv1108_clk_probe,
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};
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