mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
200 lines
5.3 KiB
Plaintext
200 lines
5.3 KiB
Plaintext
/dts-v1/;
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#include "tegra20.dtsi"
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/ {
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model = "NVIDIA Seaboard";
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compatible = "nvidia,seaboard", "nvidia,tegra20";
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chosen {
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bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
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};
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chosen {
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stdout-path = &uartd;
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};
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aliases {
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/* This defines the order of our ports */
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usb0 = "/usb@c5008000";
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usb1 = "/usb@c5000000";
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i2c0 = "/i2c@7000d000";
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i2c1 = "/i2c@7000c000";
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i2c2 = "/i2c@7000c400";
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i2c3 = "/i2c@7000c500";
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sdhci0 = "/sdhci@c8000600";
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sdhci1 = "/sdhci@c8000400";
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};
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memory {
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device_type = "memory";
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reg = < 0x00000000 0x40000000 >;
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};
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host1x {
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status = "okay";
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dc@54200000 {
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status = "okay";
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rgb {
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status = "okay";
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nvidia,panel = <&lcd_panel>;
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};
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};
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};
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/* This is not used in U-Boot, but is expected to be in kernel .dts */
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i2c@7000d000 {
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clock-frequency = <100000>;
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pmic@34 {
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compatible = "ti,tps6586x";
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reg = <0x34>;
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clk_32k: clock {
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compatible = "fixed-clock";
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/*
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* leave out for now due to CPP:
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* #clock-cells = <0>;
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*/
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clock-frequency = <32768>;
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};
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};
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};
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serial@70006300 {
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clock-frequency = < 216000000 >;
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};
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nand-controller@70008000 {
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nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
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nvidia,width = <8>;
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nvidia,timing = <26 100 20 80 20 10 12 10 70>;
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nand@0 {
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reg = <0>;
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compatible = "hynix,hy27uf4g2b", "nand-flash";
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};
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};
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i2c@7000c000 {
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clock-frequency = <100000>;
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};
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i2c@7000c400 {
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status = "disabled";
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};
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i2c@7000c500 {
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clock-frequency = <100000>;
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};
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kbc@7000e200 {
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linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
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0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
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0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
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0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
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0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
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0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
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0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
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0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
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0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
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0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
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0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
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0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
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0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
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0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
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0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
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0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
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0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
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0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
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0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
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0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
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0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
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0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
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0x1f04008a>;
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linux,fn-keymap = <0x05040002>;
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};
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emc@7000f400 {
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emc-table@190000 {
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reg = < 190000 >;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 190000 >;
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nvidia,emc-registers = < 0x0000000c 0x00000026
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0x00000009 0x00000003 0x00000004 0x00000004
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0x00000002 0x0000000c 0x00000003 0x00000003
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0x00000002 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x0000059f
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0x00000000 0x00000003 0x00000003 0x00000003
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0x00000003 0x00000001 0x0000000b 0x000000c8
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0x00000003 0x00000007 0x00000004 0x0000000f
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xa06204ae
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0x007dc010 0x00000000 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000 >;
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};
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emc-table@380000 {
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reg = < 380000 >;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 380000 >;
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nvidia,emc-registers = < 0x00000017 0x0000004b
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0x00000012 0x00000006 0x00000004 0x00000005
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0x00000003 0x0000000c 0x00000006 0x00000006
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0x00000003 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x00000b5f
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0x00000000 0x00000003 0x00000003 0x00000006
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0x00000006 0x00000001 0x00000011 0x000000c8
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0x00000003 0x0000000e 0x00000007 0x0000000f
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xe044048b
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0x007d8010 0x00000000 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000 >;
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};
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};
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usb@c5000000 {
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nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
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dr_mode = "otg";
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};
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usb@c5004000 {
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status = "disabled";
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};
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sdhci@c8000400 {
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status = "okay";
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cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
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power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
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bus-width = <4>;
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};
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sdhci@c8000600 {
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status = "okay";
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bus-width = <8>;
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};
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lcd_panel: panel {
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/* Seaboard has 1366x768 */
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clock = <70600000>;
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xres = <1366>;
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yres = <768>;
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left-margin = <58>;
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right-margin = <58>;
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hsync-len = <58>;
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lower-margin = <4>;
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upper-margin = <4>;
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vsync-len = <4>;
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hsync-active-high;
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nvidia,bits-per-pixel = <16>;
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nvidia,pwm = <&pwm 2 0>;
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nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
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GPIO_ACTIVE_HIGH>;
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nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
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GPIO_ACTIVE_HIGH>;
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nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
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GPIO_ACTIVE_HIGH>;
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nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
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GPIO_ACTIVE_HIGH>;
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nvidia,panel-timings = <400 4 203 17 15>;
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};
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};
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