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![Giulio Benetti](/assets/img/avatar_default.png)
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
317 lines
6.8 KiB
C
317 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <dm/uclass.h>
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#include <clk.h>
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#include "clk.h"
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#include <linux/err.h>
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#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
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#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
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#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
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#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
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#define PLL_NUM_OFFSET 0x10
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#define PLL_DENOM_OFFSET 0x20
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_ENABLE (0x1 << 13)
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#define BM_PLL_LOCK (0x1 << 31)
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struct clk_pllv3 {
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struct clk clk;
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void __iomem *base;
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u32 power_bit;
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bool powerup_set;
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u32 enable_bit;
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u32 div_mask;
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u32 div_shift;
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};
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#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
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static ulong clk_pllv3_generic_get_rate(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
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return (div == 1) ? parent_rate * 22 : parent_rate * 20;
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}
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static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 val, div;
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if (rate == parent_rate * 22)
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div = 1;
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else if (rate == parent_rate * 20)
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div = 0;
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else
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return -EINVAL;
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val = readl(pll->base);
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val &= ~(pll->div_mask << pll->div_shift);
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val |= (div << pll->div_shift);
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writel(val, pll->base);
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/* Wait for PLL to lock */
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while (!(readl(pll->base) & BM_PLL_LOCK))
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;
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return 0;
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}
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static int clk_pllv3_generic_enable(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 val;
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val = readl(pll->base);
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if (pll->powerup_set)
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val |= pll->power_bit;
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else
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val &= ~pll->power_bit;
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val |= pll->enable_bit;
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writel(val, pll->base);
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return 0;
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}
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static int clk_pllv3_generic_disable(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 val;
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val = readl(pll->base);
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if (pll->powerup_set)
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val &= ~pll->power_bit;
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else
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val |= pll->power_bit;
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val &= ~pll->enable_bit;
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writel(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_generic_ops = {
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.get_rate = clk_pllv3_generic_get_rate,
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.enable = clk_pllv3_generic_enable,
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.disable = clk_pllv3_generic_disable,
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.set_rate = clk_pllv3_generic_set_rate,
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};
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static ulong clk_pllv3_sys_get_rate(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 div = readl(pll->base) & pll->div_mask;
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return parent_rate * div / 2;
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}
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static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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unsigned long min_rate;
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unsigned long max_rate;
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u32 val, div;
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if (parent_rate == 0)
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return -EINVAL;
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min_rate = parent_rate * 54 / 2;
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max_rate = parent_rate * 108 / 2;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate * 2 / parent_rate;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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/* Wait for PLL to lock */
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while (!(readl(pll->base) & BM_PLL_LOCK))
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;
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return 0;
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}
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static const struct clk_ops clk_pllv3_sys_ops = {
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.enable = clk_pllv3_generic_enable,
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.disable = clk_pllv3_generic_disable,
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.get_rate = clk_pllv3_sys_get_rate,
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.set_rate = clk_pllv3_sys_set_rate,
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};
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static ulong clk_pllv3_av_get_rate(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
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u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
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u32 div = readl(pll->base) & pll->div_mask;
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u64 temp64 = (u64)parent_rate;
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if (mfd == 0)
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return -EIO;
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temp64 *= mfn;
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do_div(temp64, mfd);
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return parent_rate * div + (unsigned long)temp64;
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}
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static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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unsigned long min_rate;
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unsigned long max_rate;
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u32 val, div;
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u32 mfn, mfd = 1000000;
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u32 max_mfd = 0x3FFFFFFF;
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u64 temp64;
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if (parent_rate == 0)
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return -EINVAL;
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min_rate = parent_rate * 27;
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max_rate = parent_rate * 54;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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if (parent_rate <= max_mfd)
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mfd = parent_rate;
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div = rate / parent_rate;
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temp64 = (u64)(rate - div * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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writel(mfn, pll->base + PLL_NUM_OFFSET);
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writel(mfd, pll->base + PLL_DENOM_OFFSET);
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/* Wait for PLL to lock */
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while (!(readl(pll->base) & BM_PLL_LOCK))
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;
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return 0;
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}
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static const struct clk_ops clk_pllv3_av_ops = {
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.enable = clk_pllv3_generic_enable,
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.disable = clk_pllv3_generic_disable,
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.get_rate = clk_pllv3_av_get_rate,
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.set_rate = clk_pllv3_av_set_rate,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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{
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struct clk_pllv3 *pll;
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struct clk *clk;
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char *drv_name;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->power_bit = BM_PLL_POWER;
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pll->enable_bit = BM_PLL_ENABLE;
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switch (type) {
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case IMX_PLLV3_GENERIC:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
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pll->div_shift = 0;
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pll->powerup_set = false;
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break;
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case IMX_PLLV3_SYS:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
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pll->div_shift = 0;
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pll->powerup_set = false;
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break;
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case IMX_PLLV3_USB:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
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pll->div_shift = 1;
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pll->powerup_set = true;
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break;
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case IMX_PLLV3_AV:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
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pll->div_shift = 0;
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pll->powerup_set = false;
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break;
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default:
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kfree(pll);
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return ERR_PTR(-ENOTSUPP);
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}
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pll->base = base;
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pll->div_mask = div_mask;
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clk = &pll->clk;
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ret = clk_register(clk, drv_name, name, parent_name);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_pllv3_generic) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_generic_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(clk_pllv3_sys) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_sys_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(clk_pllv3_usb) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_USB,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_generic_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(clk_pllv3_av) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_AV,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_av_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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