mirror of
https://github.com/brain-hackers/u-boot-brain
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b84d4d0932
This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
36 lines
741 B
Makefile
36 lines
741 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2016 Google, Inc
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ifdef CONFIG_HAVE_MRC
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obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
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endif
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ifdef CONFIG_INTEL_CAR_CQOS
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obj-$(CONFIG_TPL_BUILD) += car2.o
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ifndef CONFIG_SPL_BUILD
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obj-y += car2_uninit.o
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endif
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endif
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obj-y += cpu.o
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obj-y += fast_spi.o
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obj-y += lpc.o
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obj-y += lpss.o
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ifndef CONFIG_TARGET_EFI_APP
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
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ifndef CONFIG_$(SPL_)X86_64
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obj-y += microcode.o
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endif
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endif
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obj-y += pch.o
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ifdef CONFIG_SPL
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ifndef CONFIG_SPL_BUILD
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obj-y += cpu_from_spl.o
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endif
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endif
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