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https://github.com/brain-hackers/u-boot-brain
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280057bd7d
With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
291 lines
7.2 KiB
C
291 lines
7.2 KiB
C
/*
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* (C) Copyright 2017
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/rcc.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32_periph.h>
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#define RCC_CR_HSION BIT(0)
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#define RCC_CR_HSEON BIT(16)
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#define RCC_CR_HSERDY BIT(17)
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#define RCC_CR_HSEBYP BIT(18)
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#define RCC_CR_CSSON BIT(19)
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#define RCC_CR_PLLON BIT(24)
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#define RCC_CR_PLLRDY BIT(25)
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#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
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#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
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#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
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#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
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#define RCC_PLLCFGR_PLLSRC BIT(22)
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#define RCC_PLLCFGR_PLLM_SHIFT 0
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#define RCC_PLLCFGR_PLLN_SHIFT 6
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#define RCC_PLLCFGR_PLLP_SHIFT 16
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#define RCC_PLLCFGR_PLLQ_SHIFT 24
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#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
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#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
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#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
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#define RCC_CFGR_SW0 BIT(0)
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#define RCC_CFGR_SW1 BIT(1)
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#define RCC_CFGR_SW_MASK GENMASK(1, 0)
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#define RCC_CFGR_SW_HSI 0
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#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
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#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
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#define RCC_CFGR_SWS0 BIT(2)
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#define RCC_CFGR_SWS1 BIT(3)
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#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
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#define RCC_CFGR_SWS_HSI 0
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#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
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#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_PPRE1_SHIFT 10
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#define RCC_CFGR_PPRE2_SHIFT 13
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/*
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* Offsets of some PWR registers
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*/
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#define PWR_CR1_ODEN BIT(16)
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#define PWR_CR1_ODSWEN BIT(17)
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#define PWR_CSR1_ODRDY BIT(16)
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#define PWR_CSR1_ODSWRDY BIT(17)
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struct pll_psc {
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u8 pll_m;
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u16 pll_n;
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u8 pll_p;
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u8 pll_q;
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u8 ahb_psc;
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u8 apb1_psc;
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u8 apb2_psc;
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};
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#define AHB_PSC_1 0
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#define AHB_PSC_2 0x8
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#define AHB_PSC_4 0x9
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#define AHB_PSC_8 0xA
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#define AHB_PSC_16 0xB
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#define AHB_PSC_64 0xC
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#define AHB_PSC_128 0xD
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#define AHB_PSC_256 0xE
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#define AHB_PSC_512 0xF
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#define APB_PSC_1 0
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#define APB_PSC_2 0x4
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#define APB_PSC_4 0x5
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#define APB_PSC_8 0x6
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#define APB_PSC_16 0x7
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#if !defined(CONFIG_STM32_HSE_HZ)
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#error "CONFIG_STM32_HSE_HZ not defined!"
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#else
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#if (CONFIG_STM32_HSE_HZ == 25000000)
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#if (CONFIG_SYS_CLK_FREQ == 200000000)
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/* 200 MHz */
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struct pll_psc sys_pll_psc = {
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.pll_m = 25,
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.pll_n = 400,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2
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};
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#endif
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#else
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#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
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#endif
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#endif
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int configure_clocks(void)
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{
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/* Reset RCC configuration */
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setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
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writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
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clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
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| RCC_CR_PLLON));
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writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
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clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
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writel(0, &STM32_RCC->cir); /* Disable all interrupts */
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/* Configure for HSE+PLL operation */
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setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
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while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
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;
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setbits_le32(&STM32_RCC->cfgr, ((
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sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
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| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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/* Configure the main PLL */
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uint32_t pllcfgr = 0;
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pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
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pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
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pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
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pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
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pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
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writel(pllcfgr, &STM32_RCC->pllcfgr);
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/* Enable the main PLL */
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setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
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while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
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;
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/* Enable high performance mode, System frequency up to 200 MHz */
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
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setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
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/* Infinite wait! */
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while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
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;
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/* Enable the Over-drive switch */
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setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
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/* Infinite wait! */
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while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
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;
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stm32_flash_latency_cfg(5);
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clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
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setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
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while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL)
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;
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return 0;
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}
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unsigned long clock_get(enum clock clck)
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{
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u32 sysclk = 0;
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u32 shift = 0;
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/* Prescaler table lookups for clock computation */
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u8 ahb_psc_table[16] = {
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0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
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};
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u8 apb_psc_table[8] = {
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0, 0, 0, 0, 1, 2, 3, 4
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};
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if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
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RCC_CFGR_SWS_PLL) {
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u16 pllm, plln, pllp;
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pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
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>> RCC_PLLCFGR_PLLN_SHIFT);
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pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
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>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
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sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
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}
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switch (clck) {
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case CLOCK_CORE:
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return sysclk;
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break;
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case CLOCK_AHB:
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shift = ahb_psc_table[(
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(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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>> RCC_CFGR_HPRE_SHIFT)];
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return sysclk >>= shift;
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break;
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case CLOCK_APB1:
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shift = apb_psc_table[(
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(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
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>> RCC_CFGR_PPRE1_SHIFT)];
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return sysclk >>= shift;
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break;
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case CLOCK_APB2:
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shift = apb_psc_table[(
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(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
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>> RCC_CFGR_PPRE2_SHIFT)];
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return sysclk >>= shift;
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break;
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default:
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return 0;
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break;
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}
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}
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static int stm32_clk_enable(struct clk *clk)
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{
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u32 offset = clk->id / 32;
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u32 bit_index = clk->id % 32;
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debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
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__func__, clk->id, offset, bit_index);
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setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index));
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return 0;
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}
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void clock_setup(int peripheral)
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{
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switch (peripheral) {
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case SYSCFG_CLOCK_CFG:
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setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
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break;
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case TIMER2_CLOCK_CFG:
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
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break;
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case STMMAC_CLOCK_CFG:
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setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
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setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
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setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
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break;
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default:
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break;
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}
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}
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static int stm32_clk_probe(struct udevice *dev)
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{
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debug("%s: stm32_clk_probe\n", __func__);
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configure_clocks();
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return 0;
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}
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static int stm32_clk_of_xlate(struct clk *clk,
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struct fdtdec_phandle_args *args)
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{
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debug("%s(clk=%p)\n", __func__, clk);
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if (args->args_count != 2) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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if (args->args_count)
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clk->id = args->args[1];
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else
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clk->id = 0;
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return 0;
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}
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static struct clk_ops stm32_clk_ops = {
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.of_xlate = stm32_clk_of_xlate,
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.enable = stm32_clk_enable,
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};
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static const struct udevice_id stm32_clk_ids[] = {
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{ .compatible = "st,stm32f42xx-rcc"},
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{}
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};
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U_BOOT_DRIVER(stm32f7_clk) = {
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.name = "stm32f7_clk",
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.id = UCLASS_CLK,
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.of_match = stm32_clk_ids,
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.ops = &stm32_clk_ops,
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.probe = stm32_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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