Aneesh V f1f2c3ca9f armv7: omap3: leave outer cache enabled ... Mainline kernel for OMAP3 doesn't enable L2 cache It expects L2$ to be enabled by ROM-code/bootloader. Leaving L2$ enabled can be troublesome in cases where the L2 cache is not under CP15 control, such as in Cortex-A9. This problem is explained in detail in the commit dc7100f408 However, this problem doesn't apply to Cortex-A8 because L2$ in Cortex-A8 is under CP15 control and hence the generic armv7 maintenance opertions work for it. As such we can make an exception for OMAP3 and leave the L2$ enabled when we jump to kernel. This is done by removing the strongly-linked implementation of v7_outer_cache_disable() and allowing it to fall back to the weakly linked implementation that doesn't do anything. Signed-off-by: Aneesh V <aneesh@ti.com>		2012-02-27 21:19:25 +01:00
..
board.c	armv7: omap3: leave outer cache enabled	2012-02-27 21:19:25 +01:00
clock.c	OMAP3+: Clock: Adding ehci clock enabling	2012-02-12 10:11:31 +01:00
config.mk	omap3: new SPL structure support	2011-09-30 22:00:54 +02:00
emac.c	AM35xx: add EMAC support	2011-12-06 23:59:36 +01:00
emif4.c	omap3: emif|sdrc: use a single global data define	2010-12-11 11:41:42 -05:00
lowlevel_init.S	arm: omap3: Define save_boot_params in lowlevel_init.S for SPL only	2012-02-12 10:11:22 +01:00
Makefile	OMAP3 SPL: Add identify_nand_chip function	2011-12-06 23:59:38 +01:00
mem.c	OMAP3: Change mem_ok to clear again after reading back	2011-12-06 23:59:38 +01:00
sdrc.c	OMAP3: Correct get_sdr_cs_offset mask	2012-02-12 10:11:23 +01:00
spl_id_nand.c	OMAP3 SPL: Add identify_nand_chip function	2011-12-06 23:59:38 +01:00
sys_info.c	omap3: make get_board_rev() function weak	2012-01-16 08:40:11 +01:00