mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 20:39:43 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
143 lines
3.7 KiB
C
143 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef __DDR3_INIT_H
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#define __DDR3_INIT_H
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/*
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* Debug
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*/
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/*
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* MV_DEBUG_INIT need to be defines, otherwise the output of the
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* DDR2 training code is not complete and misleading
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*/
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#define MV_DEBUG_INIT
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#ifdef MV_DEBUG_INIT
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#define DEBUG_INIT_S(s) puts(s)
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#define DEBUG_INIT_D(d, l) printf("%x", d)
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#define DEBUG_INIT_D_10(d, l) printf("%d", d)
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#else
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#define DEBUG_INIT_S(s)
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#define DEBUG_INIT_D(d, l)
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#define DEBUG_INIT_D_10(d, l)
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#endif
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#ifdef MV_DEBUG_INIT_FULL
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#define DEBUG_INIT_FULL_S(s) puts(s)
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#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
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#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
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#define DEBUG_WR_REG(reg, val) \
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{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#define DEBUG_RD_REG(reg, val) \
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{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#else
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#define DEBUG_INIT_FULL_S(s)
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#define DEBUG_INIT_FULL_D(d, l)
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#define DEBUG_INIT_FULL_D_10(d, l)
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#define DEBUG_WR_REG(reg, val)
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#define DEBUG_RD_REG(reg, val)
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#endif
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#define DEBUG_INIT_FULL_C(s, d, l) \
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{ DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
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#define DEBUG_INIT_C(s, d, l) \
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{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
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#define MV_MBUS_REGS_OFFSET (0x20000)
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#include "ddr3_hw_training.h"
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#define MAX_DIMM_NUM 2
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#define SPD_SIZE 128
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#ifdef MV88F78X60
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#include "ddr3_axp.h"
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#elif defined(MV88F67XX)
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#include "ddr3_a370.h"
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#elif defined(MV88F672X)
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#include "ddr3_a375.h"
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#endif
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/* DRR training Error codes */
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/* Stage 0 errors */
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#define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001
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/* Stage 1 errors */
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#define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001
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#define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001
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#define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003
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#define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004
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#define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005
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#define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006
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#define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007
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#define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008
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/* Stage 2 errors */
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#define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000
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typedef enum config_type {
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CONFIG_ECC,
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CONFIG_MULTI_CS,
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CONFIG_BUS_WIDTH
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} MV_CONFIG_TYPE;
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enum log_level {
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MV_LOG_LEVEL_0,
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MV_LOG_LEVEL_1,
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MV_LOG_LEVEL_2,
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MV_LOG_LEVEL_3
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};
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int ddr3_hw_training(u32 target_freq, u32 ddr_width,
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int xor_bypass, u32 scrub_offs, u32 scrub_size,
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int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl);
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void ddr3_print_version(void);
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void fix_pll_val(u8 target_fab);
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u8 ddr3_get_eprom_fabric(void);
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u32 ddr3_get_fab_opt(void);
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u32 ddr3_get_cpu_freq(void);
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u32 ddr3_get_vco_freq(void);
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int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
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u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
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u32 mask2);
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u32 ddr3_cl_to_valid_cl(u32 cl);
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u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
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u32 ddr3_get_cs_num_from_reg(void);
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u32 ddr3_get_cs_ena_from_reg(void);
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u8 mv_ctrl_rev_get(void);
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u32 ddr3_get_log_level(void);
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/* SPD */
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int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
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/*
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* Accessor functions for the registers
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*/
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static inline void reg_write(u32 addr, u32 val)
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{
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writel(val, INTER_REGS_BASE + addr);
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}
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static inline u32 reg_read(u32 addr)
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{
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return readl(INTER_REGS_BASE + addr);
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}
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static inline void reg_bit_set(u32 addr, u32 mask)
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{
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setbits_le32(INTER_REGS_BASE + addr, mask);
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}
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static inline void reg_bit_clr(u32 addr, u32 mask)
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{
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clrbits_le32(INTER_REGS_BASE + addr, mask);
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}
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#endif /* __DDR3_INIT_H */
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