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https://github.com/brain-hackers/u-boot-brain
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2b4ffbf6b4
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_LOGGING_CONFIG_H
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#define _DDR3_LOGGING_CONFIG_H
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#ifdef SILENT_LIB
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s)
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#define DEBUG_CENTRALIZATION_ENGINE(level, s)
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#define DEBUG_TRAINING_HW_ALG(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_LEVELING(level, s)
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#define DEBUG_PBS_ENGINE(level, s)
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#define DEBUG_TRAINING_STATIC_IP(level, s)
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#define DEBUG_TRAINING_ACCESS(level, s)
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#else
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#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#else
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#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
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if (level >= debug_training_bist) \
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printf s
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#define DEBUG_TRAINING_IP_ENGINE(level, s) \
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if (level >= debug_training_ip) \
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printf s
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#endif
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#endif
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/* Logging defines */
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enum mv_ddr_debug_level {
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DEBUG_LEVEL_TRACE = 1,
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DEBUG_LEVEL_INFO = 2,
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DEBUG_LEVEL_ERROR = 3,
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DEBUG_LEVEL_LAST
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};
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enum ddr_lib_debug_block {
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DEBUG_BLOCK_STATIC,
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DEBUG_BLOCK_TRAINING_MAIN,
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DEBUG_BLOCK_LEVELING,
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DEBUG_BLOCK_CENTRALIZATION,
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DEBUG_BLOCK_PBS,
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DEBUG_BLOCK_IP,
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DEBUG_BLOCK_BIST,
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DEBUG_BLOCK_ALG,
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DEBUG_BLOCK_DEVICE,
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DEBUG_BLOCK_ACCESS,
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DEBUG_STAGES_REG_DUMP,
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/* All excluding IP and REG_DUMP, should be enabled separatelly */
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DEBUG_BLOCK_ALL
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};
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int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
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int ddr3_tip_print_stability_log(u32 dev_num);
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#endif /* _DDR3_LOGGING_CONFIG_H */
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