mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
![Anup Patel](/assets/img/avatar_default.png)
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
30 lines
880 B
C
30 lines
880 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
|
*
|
|
* Copyright (C) 2018 SiFive, Inc.
|
|
* Wesley Terpstra
|
|
* Paul Walmsley
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
|
|
#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
|
|
|
|
/* Clock indexes for use by Device Tree data */
|
|
|
|
#define PRCI_CLK_COREPLL 0
|
|
#define PRCI_CLK_DDRPLL 1
|
|
#define PRCI_CLK_GEMGXLPLL 2
|
|
#define PRCI_CLK_TLCLK 3
|
|
|
|
#endif
|