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aefc0b7a60
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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.. | ||
clk_a10.c | ||
clk_a10s.c | ||
clk_a23.c | ||
clk_a31.c | ||
clk_a64.c | ||
clk_a80.c | ||
clk_a83t.c | ||
clk_h3.c | ||
clk_h6.c | ||
clk_r40.c | ||
clk_sunxi.c | ||
clk_v3s.c | ||
Kconfig | ||
Makefile |