mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
48c6f328f0
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
6 lines
147 B
Plaintext
6 lines
147 B
Plaintext
CONFIG_SPL=y
|
|
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
|
|
+S:CONFIG_PPC=y
|
|
+S:CONFIG_MPC85xx=y
|
|
+S:CONFIG_TARGET_T102XRDB=y
|