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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
199 lines
4.6 KiB
C
199 lines
4.6 KiB
C
/*
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* (C) Copyright 2004-2009
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* Texas Instruments Incorporated, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "sdp.h"
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"OMAP3 SDP3430 board",
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#if defined(CONFIG_ENV_IS_IN_ONENAND)
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"OneNAND",
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#elif defined(CONFIG_ENV_IS_IN_NAND)
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"NAND",
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#else
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"NOR",
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#endif
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};
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/* Timing definitions for GPMC controller for Sibley NOR */
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static const u32 gpmc_sdp_nor[] = {
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SDP3430_NOR_GPMC_CONF1,
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SDP3430_NOR_GPMC_CONF2,
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SDP3430_NOR_GPMC_CONF3,
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SDP3430_NOR_GPMC_CONF4,
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SDP3430_NOR_GPMC_CONF5,
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SDP3430_NOR_GPMC_CONF6,
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/*CONF7- computed as params */
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};
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/*
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* Timing definitions for GPMC controller for Debug Board
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* Debug board contains access to ethernet and DIP Switch setting
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* information etc.
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*/
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static const u32 gpmc_sdp_debug[] = {
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SDP3430_DEBUG_GPMC_CONF1,
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SDP3430_DEBUG_GPMC_CONF2,
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SDP3430_DEBUG_GPMC_CONF3,
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SDP3430_DEBUG_GPMC_CONF4,
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SDP3430_DEBUG_GPMC_CONF5,
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SDP3430_DEBUG_GPMC_CONF6,
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/*CONF7- computed as params */
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};
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/* Timing defintions for GPMC OneNAND */
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static const u32 gpmc_sdp_onenand[] = {
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SDP3430_ONENAND_GPMC_CONF1,
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SDP3430_ONENAND_GPMC_CONF2,
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SDP3430_ONENAND_GPMC_CONF3,
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SDP3430_ONENAND_GPMC_CONF4,
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SDP3430_ONENAND_GPMC_CONF5,
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SDP3430_ONENAND_GPMC_CONF6,
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/*CONF7- computed as params */
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};
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/* GPMC definitions for GPMC NAND */
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static const u32 gpmc_sdp_nand[] = {
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SDP3430_NAND_GPMC_CONF1,
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SDP3430_NAND_GPMC_CONF2,
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SDP3430_NAND_GPMC_CONF3,
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SDP3430_NAND_GPMC_CONF4,
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SDP3430_NAND_GPMC_CONF5,
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SDP3430_NAND_GPMC_CONF6,
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/*CONF7- computed as params */
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};
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/* gpmc_cfg is initialized by gpmc_init and we use it here */
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extern struct gpmc *gpmc_cfg;
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/**
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* @brief board_init - gpmc and basic setup as phase1 of boot sequence
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*
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* @return 0
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* TODO: Dynamically pop out CS mapping and program accordingly */
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/* Configure devices for default ON ON ON settings */
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enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
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CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
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enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
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GPMC_SIZE_16M);
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enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
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GPMC_SIZE_16M);
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enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
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GPMC_SIZE_16M);
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
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#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
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/**
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* @brief board_eth_init Take the Ethernet controller out of reset and wait
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* for the EEPROM load to complete.
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*/
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_LAN91C96
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int cnt = 20;
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writew(0x0, LAN_RESET_REGISTER);
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do {
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writew(0x1, LAN_RESET_REGISTER);
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udelay(100);
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if (cnt == 0)
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goto reset_err_out;
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--cnt;
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} while (readw(LAN_RESET_REGISTER) != 0x1);
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cnt = 20;
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do {
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writew(0x0, LAN_RESET_REGISTER);
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udelay(100);
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if (cnt == 0)
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goto reset_err_out;
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--cnt;
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} while (readw(LAN_RESET_REGISTER) != 0x0000);
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udelay(1000);
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writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
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udelay(1000);
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rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
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reset_err_out:
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#endif
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return rc;
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}
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/**
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* @brief misc_init_r - Configure SDP board specific configurations
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* such as power configurations, ethernet initialization as phase2 of
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* boot sequence
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*
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* @return 0
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*/
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int misc_init_r(void)
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{
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/* Partial setup:
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* VAUX3 - 2.8V for DVI
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* VPLL1 - 1.8V
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* VDAC - 1.8V
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* and turns on LEDA/LEDB (not needed ... NOP?)
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*/
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twl4030_power_init();
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/* FIXME finish setup:
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* VAUX1 - 2.8V for mainboard I/O
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* VAUX2 - 2.8V for camera
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* VAUX4 - 1.8V for OMAP3 CSI
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* VMMC1 - 3.15V (init, variable) for MMC1
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* VMMC2 - 1.85V for MMC2
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* VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
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* VPLL2 - 1.8V
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*/
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return 0;
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}
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/**
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* @brief set_muxconf_regs Setting up the configuration Mux registers
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* specific to the hardware. Many pins need to be moved from protect
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* to primary mode.
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*/
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void set_muxconf_regs(void)
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{
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/* platform specific muxes */
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MUX_SDP3430();
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}
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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