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b979e35230
The board uses T-topology for the four x16 DRAM chips, so remove the write-leveling from the SPL as that is only usefly on fly-by topology and can be harmful on T-topology. Also update the DRAM timing with values from calibration on multiple boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> |
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| dh_imx6_spl.c | ||
| dh_imx6.c | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||