mirror of
https://github.com/brain-hackers/u-boot-brain
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aac5450ea9
Boards using the TWL4030 regulator may not all use the LDOs the same way (e.g. MMC2 power can be controlled by another LDO than VMMC2). This delegates TWL4030 MMC power initializations to board-specific functions, that may still call twl4030_power_mmc_init for the default behavior. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com> [trini: Fix omap3_evm warning, add twl4030.h] Signed-off-by: Tom Rini <trini@ti.com>
193 lines
4.3 KiB
C
193 lines
4.3 KiB
C
/*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2009
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* Frederik Kriewitz <frederik@kriewitz.eu>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/mach-types.h>
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#include "devkit8000.h"
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#include <asm/gpio.h>
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#ifdef CONFIG_DRIVER_DM9000
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#include <net.h>
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#include <netdev.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static u32 gpmc_net_config[GPMC_MAX_REG] = {
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NET_GPMC_CONFIG1,
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NET_GPMC_CONFIG2,
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NET_GPMC_CONFIG3,
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NET_GPMC_CONFIG4,
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NET_GPMC_CONFIG5,
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NET_GPMC_CONFIG6,
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0
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/* Configure GPMC registers for DM9000 */
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static void gpmc_dm9000_config(void)
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{
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
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CONFIG_DM9000_BASE, GPMC_SIZE_16M);
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
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#ifdef CONFIG_DRIVER_DM9000
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uchar enetaddr[6];
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u32 die_id_0;
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#endif
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twl4030_power_init();
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#ifdef CONFIG_TWL4030_LED
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twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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/* Configure GPMC registers for DM9000 */
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
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CONFIG_DM9000_BASE, GPMC_SIZE_16M);
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/* Use OMAP DIE_ID as MAC address */
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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printf("ethaddr not set, using Die ID\n");
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die_id_0 = readl(&id_base->die_id_0);
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enetaddr[0] = 0x02; /* locally administered */
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enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
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enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
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enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
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enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
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enetaddr[5] = (die_id_0 & 0x000000ff);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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#endif
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEVKIT8000();
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
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/*
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* Routine: board_eth_init
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* Description: Setting up the Ethernet hardware.
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*/
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* Do board specific preperation before SPL
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* Linux boot
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*/
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void spl_board_prepare_for_linux(void)
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{
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gpmc_dm9000_config();
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}
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/*
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* devkit8000 specific implementation of spl_start_uboot()
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*
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* RETURN
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* 0 if the button is not pressed
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* 1 if the button is pressed
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*/
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int spl_start_uboot(void)
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{
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int val = 0;
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if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
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gpio_direction_input(SPL_OS_BOOT_KEY);
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val = gpio_get_value(SPL_OS_BOOT_KEY);
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gpio_free(SPL_OS_BOOT_KEY);
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}
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return !val;
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}
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#endif
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory. We have either one or two banks of 128MB DDR.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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/* General SDRC config */
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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/* AC timings */
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->mr = MICRON_V_MR_165;
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}
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