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https://github.com/brain-hackers/u-boot-brain
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48c6f328f0
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
/**
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
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u8 hw_ver; /* 0x02 - Hardware Revision Register */
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u8 sw_ver; /* 0x03 - Software Revision register */
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u8 res0[12]; /* 0x04 - 0x0F - not used */
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u8 reset_ctl1; /* 0x10 - Reset control Register1 */
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u8 reset_ctl2; /* 0x11 - Reset control Register2 */
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u8 int_status; /* 0x12 - Interrupt status Register */
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u8 flash_csr; /* 0x13 - Flash control and status register */
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u8 fan_ctl_status; /* 0x14 - Fan control and status register */
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u8 led_ctl_status; /* 0x15 - LED control and status register */
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u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
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u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
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u8 boot_override; /* 0x18 - Boot override register */
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u8 boot_config1; /* 0x19 - Boot config override register*/
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u8 boot_config2; /* 0x1A - Boot config override register*/
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} cpld_data_t;
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/* Pointer to the CPLD register set */
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value)\
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#define CPLD_BOOT_SEL 0x80
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