mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 14:53:44 +09:00
488b8b242b
Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
123 lines
2.7 KiB
C
123 lines
2.7 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/u-boot-x86.h>
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#include <flash.h>
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#include <netdev.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch-coreboot/tables.h>
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#include <asm/arch-coreboot/sysinfo.h>
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#include <asm/arch/timestamp.h>
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
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/*
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* Miscellaneous platform dependent initializations
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*/
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int cpu_init_f(void)
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{
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int ret = get_coreboot_info(&lib_sysinfo);
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if (ret != 0)
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printf("Failed to parse coreboot tables.\n");
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timestamp_init();
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return ret;
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_early_init_r(void)
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{
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/* CPU Speed to 100MHz */
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gd->cpu_clk = 100000000;
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/* Crystal is 33.000MHz */
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gd->bus_clk = 33000000;
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return 0;
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}
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void show_boot_progress(int val)
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{
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outb(val, 0x80);
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}
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int last_stage_init(void)
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{
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return 0;
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}
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#ifndef CONFIG_SYS_NO_FLASH
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void setup_pcat_compatibility()
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{
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}
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#define MTRR_TYPE_WP 5
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#define MTRRcap_MSR 0xfe
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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int board_final_cleanup(void)
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{
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/* Un-cache the ROM so the kernel has one
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* more MTRR available.
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*
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* Coreboot should have assigned this to the
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* top available variable MTRR.
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*/
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u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
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u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
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/* Make sure this MTRR is the correct Write-Protected type */
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if (top_type == MTRR_TYPE_WP) {
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disable_caches();
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wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
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wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
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enable_caches();
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}
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return 0;
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}
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